Memory-Logic Die Signal Routing via Wafer Bonded Wide Bus
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Solution Overview
Problem
Current memory devices face inefficiencies in data transfer between memory and logic dies, particularly when using global data buses, which can lead to reduced bandwidth and increased power consumption.
Innovation Solution
Implementing a wafer-on-wafer bonding process to directly couple memory and logic dies, allowing for high-bandwidth data transfer without the need for a global data bus, using a wide bus for efficient data routing between the memory and logic dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a global data bus is used for data transfer between memory and logic dies, then device complexity is reduced, but data bandwidth decreases and power consumption increases
Solution Approach 1:
The patent divides the monolithic data transfer structure into segmented local data buses, with each memory die having its own dedicated local bus connections to logic dies, eliminating the need for a shared global data bus and enabling parallel data transfers
Solution Approach 2:
The patent transitions from a two-dimensional global bus architecture to a three-dimensional stacked architecture with vertical inter-die connections, adding a vertical dimension to data transfer paths and enabling simultaneous multi-directional data flow
2Device complexity
If a global data bus is used for data transfer between memory and logic dies, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The patent segments the power consumption across multiple independent local data bus connections, allowing only the specific memory-logic die pairs that are actively transferring data to consume power, rather than maintaining a always-on global bus
Solution Approach 2:
The patent introduces local interface circuits as intermediaries between memory and logic dies, which manage data transfer over dedicated short-distance connections, reducing the power required compared to long-distance global bus transfers
3Productivity
If wafer-on-wafer bonding is implemented to directly couple memory and logic dies, then data bandwidth increases, but manufacturing complexity increases
Solution Approach 1:
The patent performs wafer-on-wafer bonding before the final packaging stage, allowing memory wafers and logic wafers to be bonded in advance while still on fabrication lines, which simplifies the overall manufacturing process compared to post-packaging integration
Solution Approach 2:
The patent employs self-aligned bonding techniques where corresponding pads and connection structures on memory and logic wafers automatically align during the bonding process, reducing the need for complex external alignment equipment and procedures
Data Source
AI summary
A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.