Memory-Logic Die Signal Routing via Wide-Bus Wafer Bonding
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Solution Overview
Problem
Existing memory devices face inefficiencies in data transfer between memory and logic dies, particularly when using global data buses, which limits bandwidth and increases power consumption.
Innovation Solution
Implementing a wide bus between memory and logic dies through wafer-on-wafer bonding, allowing direct data transfer without traditional I/O, utilizing transceivers on either die to enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional I/O methods are used for data transfer between memory and logic dies, then device complexity is reduced and ease of manufacture is improved, but bandwidth is limited and power consumption increases
Solution Approach 1:
The patent merges the memory die and logic die into a single integrated device through wafer-on-wafer bonding, creating a unified structure where data transfer occurs internally rather than through external I/O interfaces. This integration eliminates the need for separate I/O circuitry while providing direct high-bandwidth connections between memory and logic units, thereby resolving the contradiction between improved bandwidth and increased device complexity.
Solution Approach 2:
The patent transitions from traditional two-dimensional planar I/O interfaces to three-dimensional vertical stacking through wafer bonding. By stacking the memory die and logic die vertically and connecting them through through-silicon vias (TSVs), the patent creates high-bandwidth interconnects in the vertical dimension, enabling massive parallel data transfer without increasing lateral device footprint or I/O complexity.
2Use of energy by moving object
If traditional I/O methods are used for data transfer between memory and logic dies, then manufacturing processes are simplified, but power consumption increases due to longer data paths
Solution Approach 1:
By merging the memory die and logic die into a single bonded package, the patent dramatically shortens the data path length from external I/O traces to direct internal connections. This reduction in signal path length decreases capacitive loading and resistive losses, thereby reducing power consumption for data transfer while the bonding process itself remains compatible with existing semiconductor manufacturing techniques.
Solution Approach 2:
The patent replaces the mechanical/electrical I/O interface system with a direct semiconductor-to-semiconductor bonded interface. By substituting external I/O connectors and traces with intimate die-to-die bonding and TSV interconnects, the patent eliminates power losses associated with external signaling while maintaining manufacturability through established bonding processes.
3Productivity
If wafer-on-wafer bonding with wide bus is implemented, then bandwidth increases and power consumption reduces, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent segments the overall system into distinct functional modules (memory die, logic die, TSV interconnects) that can be fabricated separately using standard processes, then bonded together. This modular segmentation allows each component to be optimized independently while the bonding process itself remains a single integrated step, thereby achieving high bandwidth without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent performs preliminary fabrication of the memory die and logic die separately using conventional semiconductor manufacturing processes before the bonding step. By completing all complex circuit fabrication, TSV formation, and pad preparation in advance, the actual bonding process becomes a relatively simple alignment and bonding operation, thereby achieving high performance integration without overwhelming manufacturing complexity.
4Speed
If additional transceivers are incorporated to enhance data transfer rates, then bandwidth increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs the bonded interface to serve multiple functions: it provides high-speed data transfer, power delivery, and signaling capabilities through the same physical connection. By making the wide bus interface universal and multi-functional, the patent achieves enhanced data transfer rates without requiring separate dedicated transceiver circuits for each function, thereby increasing speed while limiting the growth of device complexity.
Data Source
AI summary
A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.