Memory-Logic Die Signal Routing With Wide-Bus Wafer Bonding
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Solution Overview
Problem
Existing memory devices face inefficiencies in data transfer between memory and logic dies, particularly when using global data buses, which can limit bandwidth and increase power consumption.
Innovation Solution
Implementing a wide bus between memory and logic dies through wafer-on-wafer bonding, allowing direct data transfer without going through traditional I/O, utilizing transceivers on either die to enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a global data bus is used for data transfer between memory die and logic die, then device complexity is reduced, but bandwidth is limited and power consumption increases
Solution Approach 1:
The patent segments the data transfer path by creating separate dedicated interconnects for different data types (input data, kernel data, output data) between memory die and logic die, eliminating the bottleneck of a single global data bus and enabling parallel data transfers that significantly increase bandwidth
Solution Approach 2:
The patent transitions from a two-dimensional global bus architecture to a three-dimensional stacked architecture with vertical interconnects (TSVs) enabling direct point-to-point connections between memory and logic dies, adding a vertical dimension to data transfer paths and multiplying bandwidth capacity
2Device complexity
If a global data bus is used for data transfer between memory die and logic die, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The patent extracts the data transfer function from the shared global data bus and creates dedicated interconnect structures for specific data flows, eliminating unnecessary signal routing through the global bus and reducing power consumption by enabling direct, short-distance connections between memory and logic dies
Solution Approach 2:
The patent introduces dedicated interconnect structures as intermediaries between memory die and logic die, replacing the global data bus as the mediation channel for data transfer, which reduces power consumption by providing specialized, optimized pathways for different data types
3Device complexity
If traditional I/O routing is used, then device complexity is reduced, but bandwidth is limited
Solution Approach 1:
The patent segments the signal routing into dedicated pathways for different data types (input, kernel, output) and uses separate interconnect structures for each, eliminating the contention and bandwidth limitations of traditional shared I/O routing while maintaining manageable device complexity through modular organization
Data Source
AI summary
A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.