Nonvolatile Memory Loop Status Circuit for Program Failure Detection
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Solution Overview
Problem
Nonvolatile memory devices face challenges in detecting program failures due to unintended noise during programming operations, as conventional status detecting methods are limited and may not identify uncorrectable errors effectively.
Innovation Solution
A nonvolatile memory device that generates loop status information by using a loop status circuit to detect state pass loops and determine program success, reassigning addresses based on determined loop status, and employing a control logic to manage program voltages in units of loops, allowing for the identification of program failures caused by noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional status detecting operation is used to determine whether data are programmed within limited number of program loops, then the program status can be detected, but uncorrectable errors due to noise during program operation cannot be identified
Solution Approach 1:
The patent segments the program operation into multiple program loops and introduces a loop status circuit that independently monitors each loop. This segmentation allows detection of program failures at the loop level rather than only at the final status level, enabling identification of uncorrectable errors that occur during intermediate loops due to noise or other disturbances.
Solution Approach 2:
The loop status circuit provides continuous feedback during the program operation by monitoring whether memory cells have reached target states after each program loop. This feedback mechanism enables real-time detection of program failures and allows the system to identify when programming has failed due to noise or other errors, improving overall detection precision.
2Quantity of substance
If memory cells are programmed to a plurality of target states, then data storage capacity is increased, but the ability to detect uncorrectable errors through status detecting operation is limited
Solution Approach 1:
The patent applies segmentation by dividing the monitoring process into multiple independent loop status checks, each corresponding to specific target states. The loop status circuit tracks the number of program loops required to reach each target state separately, enabling precise detection of errors even in multi-state memory cells where multiple programming phases occur.
Solution Approach 2:
The loop status circuit performs preliminary detection actions during each program loop before the final status check. By monitoring target state achievement incrementally throughout the programming process, the system can identify errors early in the programming sequence, making error detection easier despite the complexity of multi-state programming.
3Reliability
If loop status circuit is introduced to detect state pass loops and determine program success, then uncorrectable errors can be identified, but device complexity increases
Solution Approach 1:
The loop status circuit is implemented within the memory device itself, utilizing existing memory cell arrays and page buffers to perform self-diagnosis during normal programming operations. The circuit serves itself by using the same hardware resources already present in the device, minimizing additional complexity while enabling comprehensive error detection.
Solution Approach 2:
The patent merges the loop status detection function with existing memory programming circuitry. The loop status circuit integrates with the voltage generator, page buffer, and control logic that are already part of the memory device, combining multiple functions into a unified structure that reduces overall device complexity compared to adding completely separate monitoring systems.
Data Source
AI summary
A nonvolatile memory device includes a cell array comprising memory cells; a voltage generator that provides a program or verification voltage to a word line of memory cells selected from the memory cells; a page buffer that transfers write data to be programmed in the selected memory cells through bit lines and to sense whether the selected memory cells are programmed to target states, based on the verification voltage; and a control logic that controls the voltage generator such that the program voltage and the verification voltage are provided to the word line in units of multiple loops during a program operation, the control logic including a loop status circuit that detects values of state pass loops associated with the target states from a sensing result of the page buffer and determines whether the program operation is successful, based on the values of the state pass loops.