Memory Loopback Network Signal Integrity

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Solution Overview

Problem

Existing memory device monitoring techniques face challenges in maintaining signal integrity and complexity due to timing differences and component variations, which affect loopback signal transmission through multiple memory devices, leading to distorted signals and increased design complexity.

Innovation Solution

Implementing a loopback network that allows direct transmission of loopback signals from a targeted memory device to an output pin, bypassing other memory devices, and using a multiplexing selection circuit to selectively use output pins for loopback signals, thereby simplifying design and reducing signal distortion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If loopback signals are transmitted through multiple memory devices, then monitoring coverage is improved, but signal integrity deteriorates due to timing differences and component variations

Engineering Contradiction:
Improvemonitoring coverageVSAvoidsignal integrity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts the loopback signal transmission path from the data transmission path by providing a dedicated loopback network separate from the storage circuitry. This allows loopback signals to be transmitted through a dedicated path that does not suffer from the timing differences and component variations affecting data paths, thereby maintaining signal integrity while still enabling monitoring of multiple memory devices.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a loopback network as an intermediary structure between the targeted memory device and the output pin. This dedicated network acts as a mediator that transmits loopback signals without the interference present in regular data paths, preserving signal integrity while enabling comprehensive monitoring.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If dedicated loopback paths are provided for each memory device, then signal integrity is improved, but device complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoiddesign complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the loopback network with the existing memory module structure, integrating the dedicated loopback paths into the overall design rather than adding completely separate structures. This allows multiple memory devices to share the loopback network infrastructure, reducing overall complexity while maintaining dedicated transmission paths for signal integrity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The loopback network is designed to serve multiple memory devices simultaneously, providing a universal monitoring pathway that can capture signals from any targeted device. This multi-functional approach allows a single network structure to replace what would otherwise require multiple separate dedicated paths, reducing design complexity while maintaining signal integrity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10825545B2Memory device loopback systems and methods
Publication Date: 2020.11.03 MICRON TECHNOLOGY INC
  • US10825545B2 patent drawing
  • US10825545B2 patent drawing
  • US10825545B2 patent drawing

AI summary

One embodiment of the present disclosure describes a loopback network including a loopback datapath and a plurality of memory devices. The plurality of memory devices may include a first memory device coupled to a first trunk connector of the first loopback datapath via a first branch connector. The plurality of memory devices may also include a second memory device coupled to the first trunk connector of the first loopback datapath via a second branch connector. When data communicated with the first memory device is targeted by loopback parameters, the first memory device may output a first loopback data signal generated based at least in part on the first data to the first loopback datapath, and the second memory device may block output from the second memory device to the first loopback datapath.