Memory Loopback Circuit with Strobe Synthesis for Timing Verification
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Solution Overview
Problem
Existing memory loopback and diagnostic circuitry for integrated circuits is complex and expensive due to timing differences between transmit and receive data paths, making comprehensive testing challenging.
Innovation Solution
A memory loopback system with test control logic, data comparators, and strobe pattern generation logic that routes write data to a read path for comparison, generating gaps between commands and controlling timing to verify data integrity, including programmable parameters for burst control and timing adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing memory loopback circuitry is implemented to test transmit and receive data paths, then data path verification is achieved, but circuit complexity and cost increase due to timing differences between transmit and receive data
Solution Approach 1:
The patent uses a transmit data source that generates copy data identical to the write data being transmitted through the memory interface. This copy data is routed through the loopback connection to the data comparator, which compares it with the received read data. By using a simple data copying mechanism rather than complex timing synchronization circuitry, the patent achieves data path verification while minimizing circuit complexity
Solution Approach 2:
The patent segments the memory interface testing function into distinct modular components: a transmit data source for generating test data, a loopback connection for routing data, and a data comparator for verification. This segmentation allows each component to be independently implemented and tested, reducing overall system complexity while maintaining comprehensive data path verification capability
2Measurement precision
If comprehensive memory interface testing is performed with proper timing control, then testing accuracy is improved, but testing time and control complexity increase
Solution Approach 1:
The test control logic generates gaps between successive commands in advance, before the actual data transmission and comparison occurs. This preliminary timing control ensures that read data is properly synchronized with corresponding write data before comparison, improving testing accuracy without requiring complex real-time timing adjustments that would increase testing time
Solution Approach 2:
The patent implements periodic testing through the test control logic that generates commands with controlled gaps between successive operations. This periodic command structure allows the system to systematically test data paths at regular intervals, maintaining measurement precision while optimizing the overall testing time through efficient command scheduling
Data Source
AI summary
A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.