Memory Device Low-Power Entry Timing for Pending Maintenance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Memory devices face increased latency and performance degradation when entering a low power state due to incomplete maintenance operations, particularly when they are relatively dirty and receive a hibernate command before finishing pending tasks.

Innovation Solution

Implementing a dynamic interval for issuing hibernate commands based on the dirty status of the memory device, allowing pending maintenance operations to be completed before entering the low power state, thereby reducing latency and maintaining performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the memory device enters a low power state immediately upon receiving a hibernate command, then power consumption is reduced, but maintenance operations may be incomplete causing increased latency and performance degradation

Engineering Contradiction:
Improvepower consumptionVSAvoidlatency
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system checks whether maintenance operations are complete before allowing the transition to low power state. This preliminary check ensures that necessary maintenance tasks are finished prior to hibernation, preventing performance degradation while still enabling power savings.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamic waiting intervals between the hibernate command and actual state transition. The interval is adjusted based on the dirty status of the memory device - longer intervals when maintenance is needed, shorter or zero intervals when maintenance is complete, allowing flexible adaptation to current device state.

Inventive Principle:
Principle #15Dynamics

2Productivity

If the memory device waits for maintenance operations to complete before entering low power state, then performance is maintained, but power consumption increases and entry latency increases

Engineering Contradiction:
ImproveperformanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system performs a partial check of maintenance operation status rather than always waiting for complete completion. When the memory device is clean (maintenance complete), it transitions immediately without waiting. When dirty (maintenance pending), it waits appropriately. This selective approach avoids unnecessary delays while maintaining performance when needed.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the timing parameter dynamically based on the dirty status of the memory device. The waiting interval before entering low power state is adjusted as a variable parameter - extended when maintenance operations are pending, reduced or eliminated when maintenance is complete, optimizing both performance and power consumption based on current state.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If a fixed interval is used for entering low power state, then the control logic is simple, but it cannot adapt to varying maintenance operation durations causing either premature entry or unnecessary delays

Engineering Contradiction:
Improvecontrol logic complexityVSAvoidadaptability to maintenance status
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The system transitions from a static fixed interval to a dynamic adaptive interval for entering low power state. The interval is determined based on real-time assessment of maintenance operation status and dirty flag, allowing the control logic to adapt flexibly to varying maintenance durations and device states.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements a feedback mechanism where the system monitors the dirty status and maintenance operation completion state, then uses this information to determine the appropriate waiting interval before entering low power state. This closed-loop approach ensures optimal timing based on actual device conditions rather than predetermined fixed intervals.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12430045B2Dynamic interval for a memory device to enter a low power state
Publication Date: 2025.09.30 MICRON TECHNOLOGY INC
  • US12430045B2 patent drawing
  • US12430045B2 patent drawing
  • US12430045B2 patent drawing

AI summary

Methods, systems, and devices for a dynamic interval for entering a low power state are described. A memory system or device may support a low power mode, which the memory system or device may enter in response to a command from a host system. In some cases, an amount of idle time observed by the host system before issuing such a command may vary based on a status of maintenance operations for the memory system or device. Additionally or alternatively, after receiving such a command, the memory system or device may complete one or more pending maintenance operations before entering the low power mode.