Semiconductor Memory Lower Electrode Recessed Region Formation
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Solution Overview
Problem
The challenge in semiconductor memory devices is to increase capacitance while maintaining high integration and reliability, which is hindered by the bowing phenomenon and increased leakage current due to the aspect ratio of lower electrodes.
Innovation Solution
A method involving the sequential formation of mold and support layers on a substrate, followed by patterning and etching to form lower electrodes with recessed regions, and an additional etching process to reduce the width of exposed sidewalls, using silicon oxide and silicon nitride or germanium oxide materials, to enhance electrode spacing and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the aspect ratio of lower electrodes is increased to increase capacitance, then the capacitance of the capacitor is improved, but the bowing phenomenon and leakage current increase
Solution Approach 1:
The patent applies local quality by creating recessed regions at specific locations on the lower electrode (at the interface between electrode and dielectric layer) rather than uniformly modifying the entire electrode structure. This localized modification addresses the bowing phenomenon and leakage current issues at critical areas while preserving the overall high aspect ratio structure needed for capacitance.
Solution Approach 2:
The patent employs preliminary action by forming the recessed regions in the lower electrode before forming the upper electrode and completing the capacitor structure. This advance preparation prevents the bowing phenomenon from affecting subsequent processing steps and ensures proper electrode spacing is established before additional layers are added.
2Reliability
If the aspect ratio of lower electrodes is increased to increase capacitance, then the capacitance of the capacitor is improved, but the bowing phenomenon increases
Solution Approach 1:
The patent applies local quality by creating recessed regions at specific locations on the lower electrode (at the interface between electrode and dielectric layer) rather than uniformly modifying the entire electrode structure. This localized modification addresses the bowing phenomenon and leakage current issues at critical areas while preserving the overall high aspect ratio structure needed for capacitance.
Solution Approach 2:
The patent employs preliminary action by forming the recessed regions in the lower electrode before forming the upper electrode and completing the capacitor structure. This advance preparation prevents the bowing phenomenon from affecting subsequent processing steps and ensures proper electrode spacing is established before additional layers are added.
3Object-generated harmful factors
If additional etching process is performed to reduce width of exposed sidewalls, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The patent merges the additional etching step with the existing manufacturing process flow by integrating it into the sequence of layer formation and patterning operations. The etching process uses the previously formed mold and support layers as masks, combining multiple functions into a coordinated process sequence rather than adding an independent, isolated step.
Solution Approach 2:
The patent uses the mold layers and support layers as intermediary elements that enable the etching process to selectively remove material from the lower electrode sidewalls. These intermediary layers serve as temporary structures that facilitate the width reduction while protecting other areas, and are subsequently removed after serving their purpose.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the reliability of semiconductor memory devices by minimizing the bowing phenomenon and reducing leakage current, thereby improving the capacitance and integration of the devices.
Implementation Method 1
removing the second mold layer may include: wet-etching the second mold layer through the opening of the second support pattern
Implementation Method 2
Etching the exposed sidewalls of the portions the lower electrodes may include: performing a wet etching process to reduce widths of the exposed portions of lower electrodes
Data Source
AI summary
According to example embodiments of inventive concepts, method of forming a semiconductor memory devices includes sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate, forming lower electrodes penetrating the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, patterning the second support layer to form a second support pattern including an opening, removing the second mold layer to expose portions of sidewalls of the lower electrodes, and etching the exposed sidewalls of the lower electrodes.