Memory Interface Low-Voltage Threshold Tuning for Lower Latency

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Solution Overview

Problem

Memory systems with static low voltage detection (LVD) thresholds often suspend operations unnecessarily, leading to increased latency despite maintaining data integrity, particularly at varying interface speeds and inconsistent voltages.

Innovation Solution

Implementing a configurable LVD threshold that adjusts dynamically based on the interface speed of the memory system, allowing higher thresholds at high speeds and lower thresholds at low speeds to maintain data integrity without unnecessary suspensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a static LVD threshold is used, then data integrity is maintained, but operations are suspended unnecessarily increasing latency

Engineering Contradiction:
Improvedata integrityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies dynamics by transitioning from a static LVD threshold to a dynamic threshold that automatically adjusts based on interface speed. The system monitors the operational mode and modifies the threshold accordingly, allowing higher thresholds at high speeds and lower thresholds at low speeds, thereby preventing unnecessary suspensions while maintaining data integrity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes by varying the LVD threshold value based on the interface speed parameter. When the interface operates at high speed, a higher threshold is applied; when operating at low speed, a lower threshold is applied. This dynamic parameter adjustment resolves the contradiction between maintaining data integrity and avoiding unnecessary operations suspension.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a high LVD threshold is used, then data integrity is improved, but operations suspend more frequently increasing latency

Engineering Contradiction:
Improvedata integrityVSAvoidoperation continuity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically adjusts the LVD threshold based on the operational context (interface speed). At high speeds, a higher threshold ensures data integrity; at low speeds, a lower threshold prevents unnecessary suspensions. This dynamic adaptation maintains both data integrity and operation continuity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The LVD threshold parameter is changed based on the interface speed parameter. The system establishes a relationship where the threshold value varies with the operating speed, allowing optimization of both reliability and productivity by matching the threshold to the current operational conditions.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If a low LVD threshold is used, then unnecessary suspensions are reduced, but data integrity may be compromised at high speeds

Engineering Contradiction:
Improveoperation continuityVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies dynamics by making the LVD threshold adaptive rather than fixed. The threshold automatically increases when operating at high speeds to ensure data integrity, and decreases at low speeds to prevent unnecessary suspensions. This dynamic behavior resolves the contradiction between productivity and reliability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the threshold parameter based on the interface speed parameter. At high speeds, the threshold is set higher to protect data integrity; at low speeds, it is set lower to maintain operation continuity. This parameter adaptation allows simultaneous optimization of both productivity and reliability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260004853A1Configurable low voltage detection threshold at a memory system
Publication Date: 2026.01.01 MICRON TECHNOLOGY INC
  • US20260004853A1 patent drawing
  • US20260004853A1 patent drawing
  • US20260004853A1 patent drawing

AI summary

Methods, systems, and devices for configurable low voltage detection threshold at a memory system are described. The described techniques provide for a memory system to adjust a low voltage detection (LVD) threshold according to an interface speed of the memory system. The LVD threshold may be correlated with the interface speed, such that when operating at a relatively high interface speed, the memory system may set the LVD threshold to a relatively high value and when operating at a relatively low interface speed, the memory system may set the LVD threshold to a relatively low value. Additionally, or alternatively, the memory system may be configured to adjust the LVD threshold when changing an interface speed for subsequent operations. For example, the memory system may receive a command indicating a second interface speed and may set the LVD threshold to a second value that is associated with the second speed.