In-Memory MAC Operator for Neural Network Data Throughput

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Solution Overview

Problem

Deep learning neural networks require increased computational resources due to the exponential growth in data processing needs, and traditional hardware systems with separate processors and memory lead to performance degradation due to limited data communication between these components.

Innovation Solution

A PIM (Processing-In-Memory) system with integrated processors and memory, utilizing a MAC operator that includes data type converters and multipliers to perform arithmetic operations directly within the semiconductor chip, enhancing data processing speed for neural networks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional hardware systems with separate processors and memory are used, then system architecture is simple and易于制造, but data communication between memory and processor is limited causing performance degradation

Engineering Contradiction:
Improvedata processing speedVSAvoidsystem architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the processor and memory into a single integrated device, allowing arithmetic operations to be performed directly within the memory structure. This integration eliminates the need for separate data communication channels between processor and memory, thereby resolving the performance degradation caused by limited data communication while maintaining a unified system architecture.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integrated device performs multiple functions: it stores data in memory cells and simultaneously performs arithmetic operations using the stored data. The memory structure serves both as storage medium and as the basis for computational operations, enabling the system to handle both data storage and processing tasks within a single unified structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If the number of layers in neural network is increased to improve AI performance, then AI performance is improved, but the amount of computation required increases exponentially

Engineering Contradiction:
ImproveAI performanceVSAvoidcomputation resources
Core Design Contradiction:
ProductivityVSPower

Solution Approach 1:

The system performs computation directly where data is stored, eliminating the need to transfer data between separate processor and memory units. Each memory cell participates in arithmetic operations using its stored data, allowing the system to handle increased computational requirements of deeper neural networks without proportionally increasing power consumption or computational resource demands.

Inventive Principle:
Principle #25Self-service

3Speed

If PIM device performs arithmetic operations internally, then data processing speed is improved, but device structure becomes more complex

Engineering Contradiction:
Improvedata processing speedVSAvoiddevice structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent replaces traditional mechanical/electrical data transfer mechanisms with direct in-memory computation. Instead of physically moving data between separate processor and memory components, the system performs arithmetic operations directly on the data stored in memory cells, eliminating the need for complex data transfer infrastructure and reducing overall device structural complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11909421B2Multiplication and accumulation (MAC) operator
Publication Date: 2024.02.20 SK HYNIX INC
  • US11909421B2 patent drawing
  • US11909421B2 patent drawing
  • US11909421B2 patent drawing

AI summary

A MAC operator includes a plurality of data type converters and a plurality of multipliers. Each of the plurality of data type converters may receive 16-bit input data of one of first to fourth data types of a floating-point format to convert into L-bit output data of the floating-point format. Each of the plurality of multipliers may perform a multiplication on the “L”-bit output data of the floating-point format outputted from two of the plurality of data type converters to output multiplication result data of the floating-point format.