In-Memory MAC Array with Dynamic Voltage Boost for Noise Robustness
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Solution Overview
Problem
Current AI systems face limitations in efficiency, power consumption, noise margin, and latency due to binary operations and high computational intensity, particularly in in-memory computation for deep neural networks, which affects their ability for real-time, secure, and low-power local decision-making.
Innovation Solution
A reconfigurable data processing and storage unit is developed, incorporating a memory array with dynamic voltage boost and word line drivers, enabling analog operations and multibit digital-to-analog conversions within the memory array to enhance MAC operations and reduce instability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If in-memory computation is used for MAC operations, then computational efficiency is improved, but instability and noise margin deteriorate
Solution Approach 1:
The patent implements dynamic voltage boosting that activates only during MAC operations rather than continuously. The voltage boost circuit responds to control signals that detect MAC operation mode, dynamically adjusting the supply voltage to the memory array to improve computational stability only when needed, rather than maintaining elevated voltage at all times.
Solution Approach 2:
The patent changes the voltage parameter dynamically during MAC operations by applying a voltage boost to the memory array. This parameter change improves the noise margin and stability during computationally intensive operations while allowing the system to return to normal operating parameters when MAC operations are not active, thus resolving the contradiction between efficiency and stability.
2Reliability
If dynamic voltage boost is applied during MAC operations, then noise robustness is improved, but power consumption increases
Solution Approach 1:
The voltage boost is applied periodically and selectively only during MAC operations rather than continuously. The controller activates the voltage boost circuit based on detection of MAC operation modes, creating a periodic pattern of high-power and low-power states that reduces overall power consumption while maintaining noise robustness when computationally intensive operations are performed.
Solution Approach 2:
The system dynamically adjusts power consumption by enabling voltage boost only when MAC operations are detected. This dynamic power management ensures that the additional power required for improved noise robustness is consumed only during the specific operations that benefit from enhanced stability, rather than continuously increasing power consumption.
3Device complexity
If binary operations are used in current AI systems, then implementation simplicity is improved, but computational intensity and latency worsen
Solution Approach 1:
The patent makes the memory array multi-functional by enabling it to perform both traditional storage operations and MAC computations. The same memory infrastructure handles both binary data storage and analog-style computational operations, eliminating the need for separate computational units and reducing overall system complexity while improving computational efficiency.
Solution Approach 2:
The patent merges the storage function and computation function into a single integrated system. By performing MAC operations directly within the memory array rather than transferring data between separate storage and processing units, the system reduces latency and computational intensity while maintaining implementation feasibility through the use of existing memory infrastructure.
4Productivity
If data transfer to and from memory is increased, then computational capability is improved, but power consumption and latency worsen
Solution Approach 1:
The patent combines storage and computation functions into the same physical location (the memory array). By performing MAC operations directly within the memory array using the stored weight values, the system eliminates the need to transfer data between separate memory and processing units, thus reducing latency while maintaining or improving computational capability.
Solution Approach 2:
The memory array serves itself by performing computational operations using its own stored data without requiring external processing units. The weight values stored in the memory array are directly used for MAC operations within the same array, eliminating data transfer overhead and reducing latency while maintaining computational capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces instability, improves noise robustness, enables low latency and cost-efficient calculations, and increases the reconfigurability of the system, allowing for efficient MAC operations and storage while maintaining accuracy and reducing power consumption.
Implementation Method 1
a dynamic voltage boost coupled to the memory array; and a controller coupled to the plurality of word line drivers and the dynamic voltage boost, and configured to cause the dynamic voltage boost to boost the cells during a multiply accumulate operation
Data Source
AI summary
An apparatus includes a memory array. The array in turn includes a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, coupled to the plurality of word lines and the plurality of bit line pairs, and located at the plurality of cell locations. A plurality of word line drivers are coupled to the plurality of word lines, a dynamic voltage boost is coupled to the memory array, and a controller is coupled to the plurality of word line drivers and the dynamic voltage boost. The controller is configured to cause the dynamic voltage boost to boost the cells during a multiply accumulate operation.