Memory Arrangement with Macro Banks for Matrix Processing
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Solution Overview
Problem
Traditional memory architectures are not suitable for efficient and robust matrix processing in digital signal processing hardware, as they lack parallel access capabilities, leading to issues like overlapping matrices and memory fragmentation, which restrict maximum memory bandwidth.
Innovation Solution
A memory arrangement with multiple macro banks that allows flexible specification and access of matrix sizes, enabling parallel access to multiple elements in a row or column direction by partitioning the memory space into non-overlapping basic and logic matrices, with an address resolution stage transforming logic addresses into macro bank addresses and ultimately memory cell addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional linear address space memory architecture is used, then random access to any word is possible, but parallel access to multiple matrix elements is not possible and memory bandwidth is limited
Solution Approach 1:
The memory architecture is segmented into multiple macro banks (first macro bank, second macro bank, etc.), each containing multiple memory cells. This segmentation enables parallel access to multiple memory elements simultaneously across different macro banks, thereby increasing memory bandwidth while maintaining random access capability within each bank.
Solution Approach 2:
The patent introduces a multi-dimensional addressing scheme with row and column address spaces, transforming the traditional one-dimensional linear address space into a two-dimensional matrix structure. This dimensional change enables simultaneous row and column access operations, allowing parallel retrieval of multiple matrix elements in a single operation cycle.
2Adaptability or versatility
If traditional linear address space memory architecture is used, then storage of matrices is possible, but overlapping matrices and memory fragmentation occur
Solution Approach 1:
The memory space is divided into distinct macro banks with dedicated row and column address spaces. Each macro bank independently manages its matrix data, preventing overlapping between different matrices stored in different banks. This segmentation eliminates memory fragmentation and ensures data integrity for matrix operations.
Solution Approach 2:
The patent introduces an address resolution stage that acts as an intermediary between the logical matrix addressing and physical memory cell addressing. This intermediary layer translates logical row-column addresses into physical memory addresses, ensuring proper mapping and preventing overlapping or fragmentation issues when storing multiple matrices.
3Productivity
If N-dimensional addressable memory with NDA is used, then parallel access to multiple data elements is enabled, but device complexity increases
Solution Approach 1:
The complex N-dimensional addressing logic is segmented and distributed across multiple macro banks, each handling a portion of the address space. This distributes the addressing complexity across multiple simpler units rather than requiring one complex addressing unit, reducing overall device complexity while maintaining parallel access capability.
Solution Approach 2:
The patent separates the N-dimensional addressing into distinct row and column address dimensions, with independent decoders for each dimension. This dimensional separation simplifies the addressing logic by breaking down complex multi-dimensional addressing into simpler, independent one-dimensional address decoders that operate in parallel.
Data Source
AI summary
A memory arrangement is provided having a plurality of memory elements, the elements being associated with a memory space that can be addressed in a row and column fashion during a write or a read access. The memory arrangement further includes a first macro bank comprising a first plurality of memory cells comprising a first subset of the memory elements and a second macro bank comprising a second plurality of memory cells comprising a second subset of the memory elements. The memory arrangement further includes an address resolution stage for addressing the memory cells in the respective macro banks. The memory cells are arranged so that the memory space is partitioned into a plurality of non-overlapping basic matrices, whereby each basic matrix is mapped to a given macro bank and wherein the memory cells are arranged logically so that the memory space is partitioned into a plurality of non-overlapping logic matrices of a given size, each logic matrix being of a size equal or larger than a basic matrix.