Memory Macro I/O TSV Layout for Fine-Pitch 3D Stacks
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Solution Overview
Problem
Current 3D semiconductor stacks face significant input/output delay due to the displacement of through-silicon vias (TSVs) placed outside memory macros, which disrupts area efficiency and signal transmission, especially as TSV pitches become finer than 10 μm, making it challenging to accommodate TSVs within existing memory macro designs.
Innovation Solution
The integration of through-silicon vias (TSVs) is facilitated by allowing them to be placed at least partially within the input/output circuitry of memory macros, utilizing a 'feedthrough' configuration that includes keep-out zones to optimize area utilization and support finer TSV pitches without breaking down larger memory instances into smaller ones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSVs are placed outside the memory macro, then TSV displacement is avoided, but area efficiency deteriorates and I/O delay increases
Solution Approach 1:
The patent transitions from planar TSV placement (2D) to three-dimensional TSV integration (3D) by routing TSVs through the I/O circuitry layer. This vertical integration allows TSVs to pass through the I/O block in the third dimension, eliminating the need for lateral displacement and reducing I/O delay while maintaining area efficiency.
Solution Approach 2:
The patent nests TSVs within the I/O circuitry structure by creating dedicated TSV regions embedded in the I/O block. The TSVs are positioned to pass through specific regions of the I/O circuitry, effectively nesting the via structure within the existing I/O block architecture rather than placing it externally.
2Area of stationary object
If TSV pitch is reduced below 10 μm, then area efficiency improves, but difficulty of accommodating TSVs within memory macro increases
Solution Approach 1:
The patent segments the I/O circuitry into distinct functional regions, including dedicated TSV regions, logic regions, and memory interface regions. This segmentation allows fine-pitch TSVs to be systematically arranged in specific zones without interfering with other I/O functions, making it easier to accommodate sub-10 μm TSV pitches within the memory macro structure.
3Manufacturing precision
If memory macro is divided into smaller macros, then TSV pitch requirements are met, but area efficiency deteriorates due to increased overhead
Solution Approach 1:
The patent creates a universal I/O block design that can accommodate multiple TSVs with fine pitch through integrated routing structures. The shared I/O circuitry and common TSV regions allow the macro to maintain its size without requiring subdivision, as the multi-functional I/O block can handle the increased TSV density through its integrated architecture.
Data Source
AI summary
According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through an input/output circuit of the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings at least partially in an input/output circuitry of the memory macro unit based on the determined dimensions of the memory macro unit.