Memory Macro Power Reduction via Dynamic Mode Segmentation
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the decreasing operating voltages affect their performance, necessitating a solution to manage power consumption while maintaining operational efficiency.
Innovation Solution
A memory macro is designed to operate in multiple modes, including a fully-operational and a half-operational mode, utilizing an active power reduction scheme to reduce power usage by selectively turning on and off driver circuits and word line drivers, allowing for 50% power reduction without impacting data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If operating voltage is decreased to reduce power consumption, then power usage is reduced, but performance deteriorates
Solution Approach 1:
The memory macro implements dynamic operational modes that allow it to switch between fully-operational mode and half-operational mode based on power management requirements. In half-operational mode, only one memory cell array remains active while the other is placed in retention mode, enabling the system to adapt its power consumption and performance levels dynamically rather than being fixed at a single operating point
Solution Approach 2:
The patent changes the operational parameters of the memory macro by adjusting the state of different memory cell arrays and driver circuits. By transitioning from both arrays being active to one array active and one in retention mode, the system changes its power consumption parameter while maintaining data integrity, thus resolving the contradiction between power usage and performance
2Use of energy by stationary object
If driver circuits are turned off to reduce power consumption, then power usage is reduced, but data retention may be affected
Solution Approach 1:
The patent introduces a retention mode as an intermediary state between full operation and complete shutdown. When a memory cell array is placed in retention mode, it is not fully turned off but maintained in a state that preserves data with minimal power consumption. This intermediary state allows the system to reduce power usage while ensuring data retention is maintained through dedicated retention circuitry and control mechanisms
3Use of energy by stationary object
If power reduction techniques are implemented, then power consumption is reduced, but circuit complexity increases
Solution Approach 1:
The memory macro is segmented into two independent memory cell arrays, each with its own set of driver circuits. This segmentation allows the system to independently control the operational state of each array, enabling power reduction by placing one array in retention mode while keeping the other fully operational. The segmentation approach simplifies the power management architecture compared to implementing complex voltage scaling or clock gating across the entire memory macro
Data Source
AI summary
A method of operating a memory macro includes receiving a first signal indicating a first operational mode of the memory macro, receiving a second signal indicating a second operational mode of the memory macro, generating, by a first logic circuit, a third signal and a fourth signal based on the first signal and a fifth signal thereby causing a change in the first operational mode of the memory macro, and generating, by a second logic circuit, the fifth signal and a sixth signal based on at least the second signal and thereby causing a change in the second operational mode of the memory macro. The first logic circuit is coupled to a first memory cell array and a first IO circuit. The second logic circuit is coupled to a first and second set of word line driver circuits.