Memory Macro Shared Address Bus for Multiple Arrays
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Solution Overview
Problem
Existing memory macros require a wider address bus to identify wordlines in multiple memory arrays, leading to inefficient use of space and increased complexity, as they need separate address lines for each array, whereas the proposed solution allows for a single bit-string-array to identify wordlines in multiple arrays using a shared wordline driver section and control logic, reducing the number of address lines required.
Innovation Solution
The memory macro employs a control logic/address decoder section to decode address data into wordline addresses for multiple memory arrays using a shared wordline driver section, enabling a single bit-string-array to identify wordlines in both arrays, thus reducing the number of address lines needed and optimizing space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate address lines are used for each memory array, then each array can be independently addressed, but the address bus width increases and space efficiency decreases
Solution Approach 1:
The patent combines address lines from multiple memory arrays into a shared address bus. The control logic decodes a reduced set of address lines to generate wordline addresses for multiple arrays, merging the addressing function of separate arrays into a unified system that uses fewer address lines overall.
Solution Approach 2:
The shared address bus serves multiple memory arrays simultaneously, making the address lines universal rather than dedicated to single arrays. The control logic acts as a multi-functional component that distributes addresses to appropriate arrays based on decoding results.
2Adaptability or versatility
If a wider address bus is implemented to address multiple memory arrays, then all arrays can be accessed, but the space utilization and design efficiency decrease
Solution Approach 1:
The patent merges the addressing infrastructure of multiple memory arrays into a shared system. By combining address lines and using a common control logic unit, the chip area required for separate addressing circuits is eliminated, allowing more space for actual memory storage cells.
3Reliability
If separate wordline driver sections are used for each memory array, then each array has dedicated control, but the overall system complexity increases
Solution Approach 1:
The patent merges multiple wordline driver sections into a shared driver unit that serves multiple memory arrays. The control logic generates appropriate control signals to drive wordlines in different arrays, reducing the total number of driver sections while maintaining reliable control through centralized management.
Data Source
AI summary
A method for accessing two memory locations in two different memory arrays based on a single address string includes determining three sets of address bits. A first set of address bits are common to the addresses of wordlines that correspond to the memory locations in the two memory arrays. A second set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a first memory location in a first memory array. A third set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a second memory location in a second memory array. The method includes populating the single address string with the three sets of address bits and may be performed by an address data processing unit.