Memory Macro TSV Power Distribution
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Solution Overview
Problem
Existing integrated circuit (IC) packages face challenges in power distribution due to high resistance and power losses, particularly in three-dimensional (3D) stacked IC configurations, where through-silicon vias (TSVs) are used for power distribution, leading to inefficiencies in power delivery.
Innovation Solution
Incorporating TSVs that extend through memory macros, increasing TSV density and providing a low-resistance path between the front and back sides of IC dies, thereby enhancing power distribution efficiency by reducing resistance and power losses within the IC package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If TSVs are used for power distribution in 3D stacked IC configurations, then power distribution capability is improved, but resistance and power losses increase
Solution Approach 1:
The patent divides the power distribution path into multiple segments by routing TSVs through different regions of the memory macro (including through memory arrays and dummy areas). This segmentation creates multiple parallel power distribution paths, reducing the resistance and power losses in each individual path while maintaining overall power distribution capability.
Solution Approach 2:
The patent implements local quality by strategically placing TSVs in specific regions of the memory macro based on local power requirements. TSVs are positioned to serve specific memory arrays or circuit blocks, creating localized low-resistance power distribution paths where they are most needed, thereby reducing overall power losses.
2Reliability
If TSV density is increased to reduce resistance, then power distribution efficiency is improved, but device complexity increases
Solution Approach 1:
The patent makes TSVs multi-functional by designing them to serve dual purposes: (1) as power distribution conduits and (2) as structural elements that can be routed through dummy areas and memory arrays. This universality allows the same TSV infrastructure to achieve both high power distribution efficiency and reduced device complexity by eliminating the need for separate dedicated power routing structures.
Solution Approach 2:
The patent utilizes the vertical dimension by routing TSVs through the thickness of the memory die, creating three-dimensional power distribution paths. This dimensional approach allows power to be delivered efficiently from multiple sides of the die, reducing the need for dense horizontal TSV routing and thereby reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased TSV density and low-resistance path through memory macros improve power distribution efficiency, enabling more effective power delivery in IC packages, particularly in 3D stacked configurations, by reducing resistance and power losses.
Implementation Method 1
TSVs that extend both between and through memory macros... providing a low-resistance path between the front and back sides of IC dies
Data Source
AI summary
A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.