Memory Macro TSV Routing for Lower-Loss Stacked Die Power
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Solution Overview
Problem
In integrated circuit (IC) packages, power distribution through stacked IC dies faces challenges with high resistance and power losses due to limited TSV density, which hinders efficient power delivery between logic dies and substrates.
Innovation Solution
Incorporating TSVs that extend through memory macros, increasing TSV density by positioning them both between and through memory macros, thereby reducing resistance and power losses for a given memory macro size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If TSV density is increased by positioning TSVs both between and through memory macros, then resistance and power losses are reduced, but device complexity increases
Solution Approach 1:
The patent extends TSV placement from traditional positions only between memory macros to include positions through memory macros as well, utilizing the third dimension (vertical stacking) more effectively. This dimensional expansion of TSV placement options increases TSV density without requiring additional lateral space, thereby reducing resistance and power losses while managing device complexity through efficient spatial utilization.
2Productivity
If TSV density is increased for a given memory macro size, then power distribution efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the TSV placement strategy into two distinct categories: TSVs positioned between memory macros and TSVs positioned through memory macros. This segmentation allows for optimized power distribution by distributing TSVs across different spatial locations, increasing overall TSV density without requiring uniform high-precision placement throughout the entire structure, thereby managing manufacturing precision requirements.
Data Source
AI summary
An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.