Memory Management Circuitry Stall Fault Deadlock Resolution
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Solution Overview
Problem
Existing circuitry systems face deadlocks due to stall faults during memory address translation, which prevents general-purpose operating systems like Linux from enabling stall faulting, and the separate enablement of ATS and PRI features limits their combined usage.
Innovation Solution
The proposed circuitry includes a transaction interface, translation circuitry, and control circuitry that handle data handling transactions by initiating handling based on address mappings and providing fault responses, and selectively reissues transactions upon successful memory region requests, allowing for the management of translation faults without deadlocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stall faulting is enabled in memory management unit, then translation faults can be handled by software, but deadlock occurs in some scenarios
Solution Approach 1:
The patent introduces a new message type (memory region request message) as an intermediary between the upstream device and downstream device. This intermediary message type enables coordination and communication about memory region availability, allowing the system to resolve translation faults without stalling, thereby avoiding deadlock while maintaining software-controlled fault handling.
Solution Approach 2:
The patent implements preliminary action by having the upstream device send memory region requests before initiating data handling transactions. The downstream device processes these requests in advance and notifies the upstream device when memory regions become available. This preliminary notification mechanism allows transactions to proceed without stall faults, preventing deadlock while maintaining reliability.
2Reliability
If ATS and PRI facilities are used for address translation, then translation faults can be resolved, but the features cannot be enabled simultaneously
Solution Approach 1:
The patent creates a universal message passing mechanism that can handle both ATS and PRI functionality through a single unified interface. The memory region request and response messages serve multiple purposes: they enable address translation fault resolution (PRI function) while also supporting pre-fetching and buffering of address translations (ATS function). This multi-functional approach allows both features to operate simultaneously through the same message passing infrastructure.
Data Source
AI summary
Circuitry comprises a transaction interface to receive a data handling transaction from an upstream device, the data handling transaction defining a target virtual memory address in a virtual memory address space; translation circuitry to access a set of address mappings between virtual memory addresses and physical memory addresses in a physical memory address space; the translation circuitry being configured to initiate handling of the data handling transaction by a downstream device according to a target physical memory address mapped from the target virtual memory address when the set of address mappings includes an address mapping for the target virtual memory address, and to provide a transaction response to the transaction interface indicating a fault condition when the set of address mappings fails to provide an address mapping for the target virtual memory address; and control circuitry to receive a memory region request from the upstream device, requesting that a memory region in the virtual memory address space including the target virtual memory address be made available, to initiate handling of the memory region request and to provide a response to the upstream device in dependence upon the handling of the memory region request.