Memory Management Grouping Physical Erasing Units for Bad Block Replacement

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Solution Overview

Problem

Memory storage devices experience reduced data access speed and erratic operation due to bad block management methods, which require additional processing when faulty blocks are detected across different operating units, leading to inefficient replacement and data movement.

Innovation Solution

A memory management method that groups physical erasing units into management units, where each unit has a fixed number of units belonging to different planes, allowing for in-plane replacement of bad blocks and recording replacement information in a management table to improve access stability and flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bad block replacement is performed using blocks from different operating units, then faulty blocks can be replaced, but data access speed is significantly reduced

Engineering Contradiction:
Improvebad block managementVSAvoiddata access speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent divides the memory device into multiple operating units (planes, channels, or dies) and further segments them into block groups. By segmenting the replacement block selection to the same operating unit level, the patent maintains reliability for bad block replacement while minimizing cross-unit access that would slow down data operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by restricting bad block replacement to blocks within the same operating unit whenever possible. This creates a localized replacement strategy that maintains the specific performance characteristics of each operating unit, preventing the speed degradation that occurs with cross-unit access.

Inventive Principle:
Principle #3Local quality

2Speed

If bad block replacement is not performed, then data access can continue by skipping faulty blocks, but additional processing is needed due to different block group sizes

Engineering Contradiction:
Improvedata access speedVSAvoidprocessing complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by proactively replacing bad blocks with good blocks from the same operating unit before they cause access issues. This preventive approach maintains uniform block group sizes and eliminates the need for complex runtime processing to handle variable-sized groups.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameter of block replacement location from 'any available block' to 'block within the same operating unit'. This parameter change simplifies the system by maintaining consistent block group structures, reducing the processing complexity associated with variable-sized groups.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If blocks are replaced across different operating units, then replacement can be performed, but operational stability deteriorates

Engineering Contradiction:
Improveblock replacement capabilityVSAvoidoperational stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by confining bad block replacement operations to the same operating unit. This maintains the structural integrity and operational characteristics of each unit, preventing the instability that arises from mixing blocks across different units with varying performance characteristics.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent promotes homogeneity by ensuring that replacement blocks come from the same operating unit as the faulty blocks. This maintains uniformity in block group composition and operating characteristics, thereby stabilizing the overall system operation.

Inventive Principle:
Principle #33Homogeneity

Data Source

PatentUS11954329B2Memory management method, memory storage device and memory control circuit unit
Publication Date: 2024.04.09 PHISON ELECTRONICS
  • US11954329B2 patent drawing
  • US11954329B2 patent drawing
  • US11954329B2 patent drawing

AI summary

A memory management method configured for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit are provided. The rewritable non-volatile memory module includes a plurality of dies, wherein each of the dies includes a plurality of planes, each of the planes includes a plurality of physical erasing units, and a sum of a number of the planes included in the rewritable non-volatile memory module is a first number. The method includes: grouping the plurality of physical erasing units into a plurality of management units. Each of the plurality of physical erasing units included in each of the management units belongs to a different plane, and each of the management units has a second number of the physical erasing units, wherein the second number is less than the first number.