Memory Management System Thermal Data Routing
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Solution Overview
Problem
Existing memory devices face challenges in optimizing thermal effects to enhance endurance and reduce power consumption, particularly in non-volatile memory types like flash memory or phase-change memory, where temperature influences performance and longevity.
Innovation Solution
A management system and method that utilize a CPU and a hot data tracking device to selectively access data across multiple sub-chips based on temperature, copying frequently accessed data to sub-chips with higher temperatures to optimize programming speed and reduce power consumption, while managing data access and storage between container and data areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data is stored and accessed in conventional memory devices, then data access functionality is provided, but power consumption increases and endurance is reduced due to thermal effects
Solution Approach 1:
The patent changes the operational parameters of memory devices by controlling access patterns based on temperature. The management system monitors temperature and adjusts data access behavior (reading from heated vs. non-heated devices) to optimize both power consumption and endurance, transforming static memory operation into dynamic temperature-aware operation
Solution Approach 2:
The system dynamically adjusts data access strategies based on real-time temperature conditions. The CPU and management system adaptively select which memory devices to access for hot data versus original data, creating a dynamic operation mode that responds to thermal conditions to reduce overall power consumption and wear
2Use of energy by moving object
If memory devices operate at higher temperatures to reduce power consumption, then power efficiency improves, but data access speed may be affected
Solution Approach 1:
The patent segments data into two categories: hot data (frequently accessed) and original data (less frequently accessed). This segmentation allows the system to apply different access strategies - accessing hot data from heated memory devices for power efficiency, while maintaining fast access to original data from non-heated devices when needed
Solution Approach 2:
The system creates copies of hot data in memory devices that are heated to optimal temperatures. The tracking device monitors which data is frequently accessed and directs subsequent accesses to the copied versions in heated devices, balancing power efficiency with access speed requirements
3Reliability
If the system tracks and manages hot data across multiple sub-chips, then thermal effects are optimized for better endurance and power consumption, but system complexity increases
Solution Approach 1:
The patent introduces a tracking device as an intermediary component between the CPU and memory devices. This intermediary monitors data access patterns, tracks hot data locations, and directs access requests appropriately, centralizing the complexity management function and simplifying the overall system architecture
Solution Approach 2:
The system implements feedback mechanisms where the tracking device continuously monitors data access patterns and temperature conditions, then adjusts data routing decisions accordingly. This closed-loop control optimizes thermal effects and endurance while managing complexity through automated decision-making based on real-time system state
Data Source
AI summary
Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.