Hierarchical Memory Management with Type-Specific Translation Tables

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Solution Overview

Problem

Current memory management systems in computing systems do not differentiate between types of memory devices, leading to inefficient data retrieval due to time-consuming searches in memory address translation tables and lack of identification of frequently accessed memory devices.

Innovation Solution

A memory management system that includes a table correlating physical memory addresses with the type of memory device, using a translation lookaside buffer (TLB) and XLAT translation device to store access frequency and device type data, optimizing memory usage and table mapping by dynamically rearranging data across different memory types.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a memory management system uses traditional memory address translation tables (MMXT and TLB) without differentiation, then the system structure remains simple, but data retrieval becomes time-consuming and inefficient

Engineering Contradiction:
Improvedata retrieval speedVSAvoidmemory management system complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the memory management system by introducing multiple translation tables (first translation table for first type memory devices, second translation table for second type memory devices) instead of using a single unified translation table. This segmentation allows the system to quickly identify and access the appropriate translation table based on memory device type, thereby improving data retrieval speed without significantly increasing overall system complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-storing memory device type information in the translation tables alongside address mappings. When a memory access request is received, the system can immediately determine which translation table to use based on the pre-stored device type information, eliminating the need for time-consuming searches through the entire translation table structure.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If a memory management system treats all memory devices uniformly, then the system operation is simple, but it cannot identify frequently accessed memory devices or optimize memory allocation

Engineering Contradiction:
Improvememory allocation efficiencyVSAvoidmemory management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by implementing different management strategies for different types of memory devices. The system maintains separate translation tables for different memory device types, allowing each table to be optimized for its specific memory type characteristics. This enables the system to identify frequently accessed memory devices within each category and allocate resources more efficiently, rather than treating all memory devices uniformly.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of memory device classification by introducing device type as a distinguishing parameter. Instead of managing all memory devices with a single set of parameters, the system uses device type parameters to divide memory devices into different categories, enabling more precise tracking of access patterns and more effective optimization of memory allocation for each category.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If a memory management system performs comprehensive searches in translation tables, then all memory mappings can be found, but the search process becomes time-consuming and delays data retrieval

Engineering Contradiction:
Improvememory mapping accuracyVSAvoiddata retrieval time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by pre-organizing translation entries into separate tables based on memory device type. This preliminary organization allows the system to quickly narrow down the search scope to a specific translation table based on the device type, rather than searching through all possible entries. This maintains reliable and accurate memory mapping lookup while significantly reducing the time required for data retrieval.

Inventive Principle:
Principle #10Preliminary action

4Adaptability or versatility

If a memory management system does not track access frequency, then the system operation is simple, but it cannot dynamically optimize memory usage or identify frequently accessed devices

Engineering Contradiction:
Improvememory optimization capabilityVSAvoidmemory management system complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms by tracking and monitoring access frequency of memory devices within each translation table. The system uses this feedback information to dynamically adjust memory allocation and optimization strategies for different memory device types. This allows the memory management system to adapt to changing access patterns and optimize performance based on actual usage, while maintaining manageable complexity through structured tracking approaches.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP2875432B1Memory management for a hierarchical memory system
Publication Date: 2021.03.24 MICRON TECHNOLOGY INC
  • EP2875432B1 patent drawingFigure 1~2
  • EP2875432B1 patent drawingFigure 3~4
  • EP2875432B1 patent drawingFigure 5

AI summary

Disclosed are systems and methods for managing memory. A memory management system (18) may include a table having multiple virtual memory addresses (32). Each virtual memory address (32) may correspond to a physical memory address (34) and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device (34) can be used to access the memory device (20, 22, 24) when a table hit occurs.