Memory Management Unit Address Allocation for Bandwidth
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Solution Overview
Problem
In multiprocessor systems, the connection of two instruction processors to a single main storage controller results in insufficient data bandwidth, particularly for image processors, leading to potential frame dropping during video playback due to bandwidth constraints.
Innovation Solution
A processor system is designed with a first processor, a second processor, and a memory management unit that deallocates an address range from the first processor and allocates it to the second processor, ensuring sufficient bandwidth by managing memory allocation independently of the universal OS, allowing the image processing IP to exclusively use the second main storage controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two instruction processors are connected to one main storage controller, then the system structure is simplified, but the data bandwidth for each processor becomes insufficient
Solution Approach 1:
The patent divides the address space into two separate regions: a first address space mapped to the first main storage controller and a second address space mapped to the second main storage controller. This segmentation allows each processor to have dedicated access paths to different storage controllers, resolving the bandwidth contention issue while maintaining architectural simplicity.
Solution Approach 2:
The patent introduces address space as an additional dimension for resource allocation. By mapping different address ranges to different storage controllers, the system creates parallel data access paths without adding physical connection complexity, effectively increasing bandwidth capacity through virtual addressing dimensions.
2Ease of operation
If the universal OS manages memory allocation, then the system is easier to operate, but the image processor cannot secure sufficient dedicated bandwidth
Solution Approach 1:
The patent segments memory management responsibilities between the universal OS and the image processing driver. The OS manages general memory allocation, while the driver independently manages the second address space for image processing, ensuring dedicated bandwidth without compromising operational ease.
Solution Approach 2:
The image processing driver acts as an intermediary between the universal OS and the second main storage controller. It receives memory allocation requests, translates them into address space mappings, and manages the dedicated bandwidth independently, preserving both ease of operation and performance guarantees.
3Device complexity
If the image processor shares the main storage controller with other processors, then the device complexity is reduced, but frame dropping occurs during video playback
Solution Approach 1:
The patent segments the storage controller access paths by creating separate address spaces. The first address space is exclusively mapped to the first main storage controller for general processing, while the second address space is mapped to the second main storage controller for image processing, eliminating shared access conflicts that cause frame dropping.
Solution Approach 2:
The patent performs preliminary address space allocation and mapping during system initialization. The second address space is pre-assigned to the image processing driver, ensuring that when video playback begins, the dedicated bandwidth is already in place and ready to prevent frame dropping immediately.
Data Source
AI summary
A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor.