Memory Management Unit Dynamic Data Migration

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In computer systems, the lack of awareness by the processor about how memory for various processes is mapped to different memory devices leads to significant delays when accessing data from slower memory devices, causing processes to run slowly due to inadequate memory access speed.

Innovation Solution

The system uses metadata to store and manage memory device latencies, allowing the processor to allocate processes to memory devices based on priority and access patterns, automatically transferring data between DRAM, NVRAM, and NAND flash to ensure fast memory access, thereby optimizing memory allocation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is stored in slower memory devices (NVRAM, NAND flash) to increase storage capacity, then storage capacity is improved, but memory access speed deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidmemory access speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The memory system is segmented into multiple memory devices with different characteristics (DRAM for fast access, NVRAM for medium speed and persistence, NAND flash for high capacity). The processor and memory management unit dynamically allocate different data segments to appropriate memory devices based on access patterns and priority, allowing the system to achieve both high capacity and fast access for critical data simultaneously.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If the processor is unaware of memory device mapping to simplify memory management, then ease of operation is improved, but process execution speed deteriorates due to delays

Engineering Contradiction:
Improvememory management simplicityVSAvoidprocess execution speed
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

A memory management unit acts as an intermediary between the processor and multiple memory devices. The MMU maintains mapping information and handles memory allocation transparently, so the processor remains unaware of the complexity while the MMU optimizes data placement and access patterns to minimize delays and maximize execution speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If data is automatically transferred between memory devices to optimize access speed, then memory access speed is improved, but device complexity increases

Engineering Contradiction:
Improvememory access speedVSAvoidmemory system complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The memory management unit implements self-service mechanisms by automatically monitoring access patterns and dynamically transferring data between memory devices without external intervention. The system self-optimizes by identifying frequently accessed data and moving it to faster memory devices, reducing manual configuration complexity while maintaining high access speeds.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20240152464A1Mapping non-typed memory access to typed memory access
Publication Date: 2024.05.09 MICRON TECHNOLOGY INC
  • US20240152464A1 patent drawing
  • US20240152464A1 patent drawing
  • US20240152464A1 patent drawing

AI summary

A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).