Memory Management Unit for Mixed Volatile Nonvolatile Memory Access

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Solution Overview

Problem

Conventional memory management systems experience inefficiencies due to the mixed connection of short-access-time DRAM and long-access-time NAND-type flash memory to a processor's memory bus, leading to a useless halt condition that hampers memory access efficiency.

Innovation Solution

A memory management unit that integrates management of NAND-type flash memory and DRAM within a flat memory hierarchy, using a page table and error flags to manage data access, allowing simultaneous access to both types of memory without halting other processes during data transfer from NAND to DRAM.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If DRAM and NAND-type flash memory are connected to the same memory bus, then memory capacity is increased, but access efficiency deteriorates due to halting during data transfer

Engineering Contradiction:

Improvememory capacityVSAvoidmemory access efficiency

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The memory management unit segments the unified memory space into DRAM regions and NAND flash regions, allowing independent access control. When data is accessed in the DRAM region, the system can immediately respond without waiting for NAND flash operations, thus maintaining high access efficiency while preserving the expanded memory capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory management unit acts as an intermediary between the processor and the mixed memory system. It intercepts memory access requests, determines whether the target address is in DRAM or NAND flash, and manages data transfer accordingly. This intermediary function prevents the processor from halting during NAND flash operations by handling data transfer in the background.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If data transfer from NAND to DRAM is performed, then data availability is improved, but processor halt time increases

Engineering Contradiction:

Improvedata availabilityVSAvoidprocessor halt time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The memory management unit performs preliminary actions by pre-fetching data from NAND flash to DRAM before the processor needs it. It monitors access patterns and initiates data transfer in advance, so that when the processor requests the data, it is already available in the fast DRAM, eliminating processor halts and ensuring data availability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system maintains continuity of useful action by allowing the processor to continue executing other tasks while data transfer from NAND flash to DRAM is performed in the background. The memory management unit manages this parallel operation, ensuring that data transfer does not interrupt processor operations and that data becomes available when needed.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS8589639B2Memory management unit and memory management method for controlling a nonvolatile memory and a volatile memory

Publication Date: 2013.11.19 KIOXIA CORP

AI summary

According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory.