Memory Manager Hash Address Translation CPU Overhead

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The delay in data processing in CPUs due to slower external memory speeds is exacerbated by the overhead of translating virtual addresses into physical addresses, which is inefficient and power-intensive, especially with increasing data volumes.

Innovation Solution

A memory manager with a V2H table and hash function module that translates virtual addresses into physical addresses using a hash function, reducing the need for CPU-based translation and minimizing power consumption by reducing TLB-like exception mapping table accesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If virtual address to physical address translation is performed by CPU, then address translation accuracy is ensured, but CPU overhead increases and processing speed decreases

Engineering Contradiction:
Improveaddress translation accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The address translation function is extracted from the CPU and relocated to the memory controller. The memory controller independently performs virtual-to-physical address translation using a translation buffer and hash function, removing the translation overhead from the CPU's critical path while maintaining accurate translation through dedicated translation logic.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

A translation buffer is introduced as an intermediary structure between the memory controller and external memory. This buffer caches address translation information and uses hash functions to quickly determine whether translation is needed, acting as a mediator that resolves address translation requests without requiring full CPU intervention for each memory access.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If translation buffer size is increased to reduce hash function accesses, then miss rate decreases, but memory manager size and power consumption increase

Engineering Contradiction:
Improveaddress translation success rateVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

Instead of implementing a complete address translation buffer for all possible virtual addresses, the system uses a partial translation buffer that stores only frequently accessed translations. For addresses not in the buffer, a hash function provides a probabilistic check to determine if translation is needed, performing partial action rather than exhaustive translation for every address.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system changes the parameter of address translation from deterministic (checking all addresses) to probabilistic (using hash function with configurable threshold). By adjusting the hash function parameters and translation buffer size, the system optimizes the balance between translation accuracy and power consumption based on workload characteristics.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If hash function is used for address translation, then processing speed increases and power consumption decreases, but translation accuracy may be compromised

Engineering Contradiction:
Improveaddress translation speedVSAvoidaddress translation accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The traditional mechanical address translation mechanism (sequential buffer checking) is replaced with a hash function-based computational approach. The hash function rapidly computes potential translation candidates using bitwise operations, substituting the mechanical scanning process with faster mathematical computation while maintaining accuracy through verification logic.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system implements feedback control in the address translation process. The hash function generates a preliminary translation result, which is then verified against the translation buffer and exception mapping table. This feedback loop ensures that even though the hash function provides a fast initial answer, the final translation accuracy is confirmed through verification before memory access proceeds.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11397689B2Memory manager having an address translation function, data processing structure including the same, and method for generating address translation information
Publication Date: 2022.07.26 MIMIRIP LLC
  • US11397689B2 patent drawing
  • US11397689B2 patent drawing
  • US11397689B2 patent drawing

AI summary

A memory manager includes an internal memory and a hash function circuit.The internal memory includes a V2H (virtual address to hash function) table and an exception mapping table. The V2H table stores at least one virtual address group and a type information on a hash function mapped to the virtual address group. The exception mapping table stores at least one exception virtual address not translated into a physical address by the hash function in the virtual address group and a physical address mapped to the exception virtual address. The has function circuit checks, when a virtual address is provided from a host, type information on a hash function mapped to a virtual address group including the virtual address, by referring to the V2H table included in the internal memory. The has function translates the virtual address into a physical address by using the hash function corresponding to the type information.