Memory-Mapped Off-Chip Memory for Low-Power MCU OPC UA Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Highly integrated, low-power microcontroller units (MCUs) in industrial systems face challenges in adapting to the OPC UA standard due to memory and power constraints, which limits their ability to access cloud platforms like OPC Unified Architecture (OPC UA).
Innovation Solution
Implementing memory-mapped memory configurations that allow a highly integrated, low-power microcontroller-based instrument to access off-MCU memory connected to a central processor unit (CPU) via an interface, effectively extending the on-MCU memory range, enabling the use of complex applications or protocols such as OPC UA through serial transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a highly integrated, low-power MCU is used in the microcontroller-based instrument, then power consumption is reduced and integration is improved, but memory capacity becomes insufficient for complex applications like OPC UA
Solution Approach 1:
The memory system is segmented into on-MCU memory (for critical code and data) and off-MCU memory (for bulk storage and complex protocol handling). The memory-mapped interface allows the MCU to access off-MCU memory as if it were on-chip memory, enabling segmentation of memory functions while maintaining unified access semantics.
Solution Approach 2:
A memory-mapped interface acts as an intermediary between the MCU and off-MCU memory, translating MCU memory access requests into appropriate external memory operations. This intermediary enables the MCU to access extended memory capacity without requiring direct physical connection to all memory resources.
2Adaptability or versatility
If OPC UA protocol is implemented in the microcontroller-based instrument, then cloud connectivity and standardization are improved, but memory requirements exceed the capabilities of highly integrated, low-power MCUs
Solution Approach 1:
The OPC UA implementation is segmented between on-MCU components (protocol stack core, critical data structures) and off-MCU memory (protocol buffers, large data structures, cloud communication data). This segmentation allows the instrument to support the memory-intensive OPC UA protocol while maintaining the low-power benefits of a compact MCU.
Solution Approach 2:
The solution moves from a single-dimension memory architecture (on-chip only) to a multi-dimensional memory architecture that combines on-chip and off-chip memory resources. This dimensional expansion provides the necessary memory capacity for OPC UA while preserving the advantages of highly integrated MCUs.
3Quantity of substance
If off-MCU memory is accessed using traditional memory-mapped methods, then memory capacity is extended, but the number of required pins increases, complicating the interface
Solution Approach 1:
The memory-mapped interface merges address bus, data bus, and control signal functions into a unified communication protocol that uses minimal pins. By combining multiple functions into shared signal lines and using memory-mapped I/O techniques, the interface achieves extended memory access capability with reduced pin count compared to traditional parallel memory interfaces.
Solution Approach 2:
The memory-mapped interface is designed with multi-functionality, allowing the same pins to serve multiple purposes (addressing, data transfer, control) depending on the operational phase. This universal interface design reduces the total number of pins required while maintaining full memory access capability.
Data Source
AI summary
Systems and methods for using memory-mapped memories in a microcontroller-based instrument are provided herein. The method includes operating the microcontroller-based instrument using a complex application or protocol and operating a highly integrated, low-power microcontroller unit (MCU). The MCU is configured to use memory mapping for accessing at least one off-MCU memory connected to the MCU by at least one interface. The MCU's memory-mapping configuration enables the off-MCU memory(ies) to behave as an extension of at least one on-MCU memory that is connected directly to the CPU to effectively extend a range of the at least one on-MCU memory, wherein the effective extended range of the at least one on-MCU memory enables the microcontroller-based instrument to utilize the complex application or protocol. The method further includes writing addresses and/or data to and/or reading addresses and/or data from the off-MCU memory using serial transmission during a memory mapped transaction.