Memory-Mapped Interface for Neural Network Address Translation
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Solution Overview
Problem
Traditional computing systems face inefficiencies in communication between memory-mapped and message passing systems, particularly in neurosynaptic systems where spike-based information transmission leads to power consumption and latency due to fixed tick times and sequential neuron processing.
Innovation Solution
A memory-mapped interface is developed to translate memory addresses into neural network addresses, enabling efficient data transfer between memory-mapped and message passing systems, allowing for seamless integration and reducing latency by minimizing data travel distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If spike-based information transmission is used in neurosynaptic systems, then communication between neural network processing cores is achieved, but power consumption increases and latency occurs due to fixed tick times and sequential neuron processing
Solution Approach 1:
The patent introduces a memory-mapped interface as an intermediary component that bridges the message passing system and traditional memory-mapped systems. This interface includes address translation logic that converts memory addresses to neural network addresses, enabling efficient data transfer without requiring spike-based transmission for all operations. The intermediary handles address translation and data routing, reducing the need for sequential spike processing and thereby lowering power consumption while maintaining communication speed.
2Speed
If spike-based information transmission is used in neurosynaptic systems, then communication between neural network processing cores is achieved, but latency increases due to fixed tick times and sequential neuron processing
Solution Approach 1:
The memory-mapped interface acts as a mediator that enables direct address translation and data transfer between traditional systems and the neural network processing cores. By providing this intermediary layer, the system can bypass the fixed tick time constraints and sequential processing requirements of pure spike-based transmission, thereby reducing latency while maintaining communication capability.
Solution Approach 2:
The address translation function is performed in advance by the memory-mapped interface before data transfer to the neural network cores. This preliminary action of converting memory addresses to neural network addresses eliminates the need for sequential address resolution during spike processing, thereby reducing latency in data transfer operations.
3Productivity
If direct access to input and output buffers through memory maps is implemented, then communication efficiency is enhanced and power consumption is reduced, but system complexity increases due to address translation requirements
Solution Approach 1:
The memory-mapped interface is designed to perform multiple functions: address translation from memory addresses to neural network addresses, data routing between traditional and neuromorphic systems, and buffer management. By consolidating these functions into a single universal interface component, the patent reduces overall system complexity compared to having separate dedicated components for each function, while still enabling direct access to input and output buffers through memory maps.
Data Source
AI summary
Memory-mapped interfaces for message passing computing systems are provided. According to various embodiments, a write request is received. The write request comprises write data and a write address. The write address is a memory address within a memory map. The write address is translated into a neural network address. The neural network address identifies at least one input location of a destination neural network. The write data is sent via a network according to the neural network address to the at least one input location of the destination neural network. A message is received via the network from a source neural network. The message comprises data and at least one address. A location in a buffer is determined based on the at least one address. The data is stored at the location in the buffer. The buffer is accessible via the memory map.