Multi-Phase Memory-Mapped Queue for Flash Access Control
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Solution Overview
Problem
Existing memory devices with MLC flash memory face instability issues and increased complexity due to the need for multiple hardware engines and message queues, leading to higher costs and potential side effects.
Innovation Solution
A method utilizing a multi-phase memory-mapped queue that allows for message queuing between processors and hardware engines, enabling efficient access control by sharing a single memory-mapped ring buffer across multiple phases, reducing complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple hardware engines and message queues are implemented to ensure reliable access control, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple message queues into a single shared message queue that is accessed by multiple hardware engines. This consolidation reduces the overall number of queues and associated control logic, thereby decreasing device complexity while maintaining the reliability needed for flash memory access control
Solution Approach 2:
The shared message queue is designed to serve multiple hardware engines simultaneously, making it a universal resource that performs multiple functions. This multi-functional approach eliminates the need for separate dedicated queues for each engine, reducing complexity while preserving access control reliability
2Reliability
If multiple hardware engines are implemented to achieve more reliable processing, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
By merging multiple message queues into a single shared queue, the patent reduces the total component count in the hardware architecture. Fewer components mean simpler manufacturing processes, lower assembly costs, and reduced Bill of Materials (BOM) costs, while the multiple hardware engines continue to provide reliable processing
3Device complexity
If a single memory-mapped queue is shared across multiple phases, then device complexity is reduced, but measurement precision of memory access timing may worsen
Solution Approach 1:
The shared message queue is segmented into multiple phases or stages, each handling specific types of memory access operations. This segmentation allows for precise tracking and timing of different access types while maintaining a unified queue structure, thus preserving measurement precision without increasing overall complexity
Data Source
AI summary
A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.