Memory Mapped Write Transactions for Trace Data Export
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Solution Overview
Problem
Current trace data collection methods in complex System on Chip (SoC) designs face challenges in efficiently managing trace buffers, particularly in high-performance computing environments where internal buffers impact system performance and external buffers are difficult to install, leading to limitations in debugging and performance optimization.
Innovation Solution
Implementing a system that uses memory mapped write transactions to transfer trace data from a temporary buffer on one SoC to a recording buffer on another SoC via high-speed data links, allowing direct memory access and addressing the limitations of both internal and external trace receivers by creating a unified remote and local memory space for trace data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If internal trace buffers are used in SoC, then trace data collection is enabled, but system performance is degraded
Solution Approach 1:
The patent extracts the trace buffer functionality from the main SoC system by implementing a separate remote trace receiver that collects trace data through memory-mapped I/O. This separation allows the trace buffer to reside in external memory rather than consuming internal SoC resources, thereby eliminating the performance degradation caused by internal buffers while maintaining full trace data collection capability.
2Productivity
If external trace receivers are used, then system performance is maintained, but installation becomes difficult in field-deployed systems
Solution Approach 1:
The patent implements a universal trace collection mechanism that works across multiple SoC configurations through standardized memory-mapped I/O interfaces. The remote trace receiver can be installed in various field-deployed systems without requiring custom hardware modifications, as it utilizes existing memory-mapped communication protocols already present in the SoC architecture, thereby achieving both performance maintenance and installation ease.
3Reliability
If trace buffers are implemented in deployed systems, then debugging capability is enabled, but device complexity increases
Solution Approach 1:
The patent introduces a remote trace receiver as an intermediary component that mediates between the SoC and the debugging host. This intermediary handles all trace data collection and buffering operations remotely, allowing the SoC to maintain its original simple architecture while still enabling comprehensive debugging capabilities through the intermediary's buffer management and data transfer functions.
Data Source
AI summary
A method for easily tracing the execution of an application in a computer system having a plurality of computing nodes interconnected by high speed data links is disclosed. While executing the application on one or more of the computing nodes, trace data is collected into a separate temporary trace buffer coupled to each computing node. A trace transfer request event may be generated after collecting a portion of the trace data. The trace data is recorded on a designated recording and analysis computing node by transferring the trace data from each trace buffer to a recording buffer in the designated recording node in response to the transfer request by performing memory mapped write transfers initiated by each computing node that has collected trace data. The address of the recording buffer is memory mapped into an address space of each computing node that has collected trace data.