Semiconductor Memory Mapping Factor for Decoder Degradation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor memory devices like DRAM experience reliability issues due to the degradation of the word line decoder circuit, existing solutions require increasing the device size or adding sequential circuits, which is costly and inefficient.
Innovation Solution
The implementation of a semiconductor memory system that includes a mapping factor generating unit using random number generators and controllers to generate and apply pseudo-random or initial data as mapping factors to the memory array, enhancing encryption and reducing degradation without increasing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential circuits are added to ensure path function reliability, then reliability is improved, but device area increases
Solution Approach 1:
The patent changes the addressing parameters by introducing a mapping factor that randomly maps logical addresses to physical addresses. This parameter transformation allows the system to achieve reliability without adding sequential circuits, as the mapping factor dynamically distributes access patterns across the memory array.
Solution Approach 2:
The mapping factor serves as an intermediary between the logical address and the physical address. Instead of directly accessing the memory array with sequential addresses, the system uses the mapping factor as a mediator to transform addresses, thereby preventing direct degradation of the word line decoder circuit.
2Reliability
If auxiliary cascade transistor is added to limit drain-source voltage, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces the mechanical/electrical solution (auxiliary cascade transistor) with an information-theoretic solution (mapping factor). Instead of using additional transistors to control voltage, the system uses address transformation to distribute access patterns, thereby eliminating the need for expensive additional components.
3Quantity of substance
If feature size is reduced, then integration density is improved, but reliability degradation becomes more pronounced
Solution Approach 1:
The patent introduces dynamic address mapping using the mapping factor that changes with each access operation. This dynamic transformation ensures that even as feature size is reduced and integration density is increased, the system maintains reliability by continuously redistributing access patterns to prevent localized degradation of the word line decoder circuit.
Data Source
AI summary
A semiconductor memory is provided. The memory includes: a memory array; a row address processing unit configured to output a row address; a bank address processing unit configured to output a bank address; a column address processing unit configured to output a column address; and a mapping factor generating unit, configured to generate a mapping factor, wherein an output of the mapping factor generating unit is coupled to at least one of an output of the row address processing unit, an output of the bank address processing unit, and an output of the column address processing unit, and the output of the mapping factor generating unit is further coupled to the memory array, and wherein the memory array receives a result from logical processing performed on the mapping factor and at least one of the row address, the bank address, and the column address. The technical solutions of the embodiments of the present invention can improve the security, service life and reliability of the semiconductor memory.