Memory Expansion Mapping Module for Rank Constraints
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Solution Overview
Problem
Conventional main memory systems face limitations in expanding memory capacity due to constraints on the number of physical ranks directly attachable to the memory controller, necessitating innovative methods to map logical memory locations to physical memory devices effectively.
Innovation Solution
The system employs a mapping module that maps logical memory addresses to physical memory addresses, using a map and control unit to manage memory commands and data flow, and field effect transistors (FETs) as switches to connect communication channels to sub-channels, allowing for the distribution of memory commands across multiple physical ranks and accounting for latency differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more physical ranks are directly attached to the memory controller, then memory capacity is improved, but device complexity and physical constraints are worsened
Solution Approach 1:
The patent introduces a mapping module as an intermediary component between the memory controller and physical memory ranks. This mapping module receives logical memory addresses from the memory controller and translates them to physical memory addresses, enabling the system to access more memory capacity than the number of directly attached physical ranks would normally allow. The mapping module effectively mediates the interaction between the constrained memory controller interface and the expanded physical memory resources.
Solution Approach 2:
The patent adds an address translation dimension to the memory access path. Instead of directly mapping logical addresses to physical ranks in a one-to-one manner, the system introduces an address translation layer that maps logical addresses through multiple possible physical rank combinations. This dimensional transformation allows the system to present a larger virtual memory space than the physical constraints would normally permit.
2Adaptability or versatility
If memory addresses are mapped to physical memory devices, then memory expansion capability is improved, but address mapping complexity is worsened
Solution Approach 1:
The mapping module operates autonomously to perform address translation without requiring external intervention or complex configuration. The system self-manages the mapping process by automatically translating logical addresses to physical addresses and routing memory commands to the appropriate physical ranks. This self-service approach simplifies the overall system architecture despite the complexity of the mapping function.
Solution Approach 2:
The patent extracts the address mapping function from the memory controller itself and places it in a separate mapping module. This extraction allows the memory controller to maintain its original simple interface while the complex mapping operations are handled by the dedicated mapping module, which can be configured and optimized independently.
3Quantity of substance
If memory commands are distributed across multiple physical ranks, then memory access capacity is improved, but command distribution complexity is worsened
Solution Approach 1:
The patent segments memory commands and distributes them across multiple physical ranks through the mapping module. The mapping module divides the address translation task into segments, routing different portions of memory access to different physical ranks as needed. This segmentation allows efficient utilization of multiple physical ranks while managing the complexity of command distribution through modular address translation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient memory expansion by allowing more memory devices to be accessed beyond physical rank limitations, improving memory system capacity and error detection capabilities while maintaining transparent operation to the memory controller.
Implementation Method 1
field effect transistors (FETs) as switches to connect communication channels to sub-channels
Data Source
AI summary
This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.