Memory Controller Hardware Mapping Updates for Garbage Collection
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Solution Overview
Problem
The efficiency and stability of memory controllers are compromised due to the need for complex software updates and resource occupation during operations like write, erase, and garbage collection, leading to potential software errors and reduced performance.
Innovation Solution
Implementing an acceleration processing circuit within the memory controller to autonomously update mapping and valid data tables, reducing processor resource occupation and eliminating software-dependent updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor executes software to manage data operations in the memory device, then the memory controller can perform various control functions, but the processor resource occupation increases and working efficiency decreases
Solution Approach 1:
The memory controller is designed to autonomously manage data operations including reading, writing, and erasing data in the memory device without requiring continuous processor intervention. The controller independently handles address translation, data validation, and operation scheduling, enabling the system to self-manage memory operations and reduce dependency on processor resources.
Solution Approach 2:
The patent replaces software-based processor control with hardware-based automatic control mechanisms. The memory controller uses dedicated hardware circuits for address translation, data buffering, and operation management, substituting the mechanical/software execution model with an optimized hardware control model that improves efficiency and reduces processor burden.
2Productivity
If the memory controller manages data operations efficiently, then the performance improves, but the complexity of managing mapping tables and valid data increases
Solution Approach 1:
The memory controller architecture is segmented into distinct functional modules: a processor for high-level control, a buffer memory for temporary data storage, and dedicated hardware circuits for address translation and operation management. This segmentation allows each module to handle specific tasks independently, reducing the overall management complexity while maintaining high performance.
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between the processor and the memory device. This buffer acts as a mediator that temporarily stores data and mapping information, reducing the direct management burden on the processor and simplifying the coordination between different components of the memory system.
3Reliability
If software is used to control memory operations, then flexibility is maintained, but software errors may occur and stability decreases
Solution Approach 1:
The patent replaces software-based control with hardware-based control for critical memory operations. The memory controller uses dedicated hardware circuits to execute read, write, and erase operations, eliminating software interpretation layers and potential software errors. This hardware-level control enhances system stability and reliability while reducing the complexity of software management.
4Productivity
If the feature size of semiconductor devices shrinks and integration density increases, then the performance becomes more powerful, but the difficulty of managing data operations and maintaining stability increases
Solution Approach 1:
The memory controller is divided into specialized functional units that handle different aspects of data operation management independently. This segmentation allows the system to manage complex high-density memory operations through modular, manageable components, reducing the difficulty of controlling and monitoring operations as integration density increases.
Data Source
AI summary
The present disclosure discloses memory controllers, operation methods thereof, and memory systems. The memory controller comprises: a first buffer configured to buffer a valid data table and mapping information to be updated, wherein the valid data table is to record a plurality of valid transmission unit counts, the valid transmission unit count indicates the number of transmission units that store valid data in a corresponding block, the mapping information to be updated comprises at least one piece of mapping information from a logical address to a physical address, and each transmission unit corresponds to one physical address; a second buffer configured to buffer a mapping table, wherein the mapping table is to record a plurality of pieces of mapping information; and an acceleration processing circuit configured to: update the mapping table based on the mapping information; and update the valid data table based on the mapping information to be updated.