Semiconductor Memory Margin Testing via Sense Amplifier Gain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory testing methods fail to accurately quantify the margin in read operations, leading to potential data errors and inefficient use of redundant memory cells, which can increase load capacitance and slow access times.
Innovation Solution
A semiconductor memory device and testing method that includes a redundant memory cell with margined data, allowing for quantitative comparison with regular memory cells to detect abnormalities and function as a backup, while minimizing load influence and layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing testing methods add test memory cells or non-selected bit lines to increase load capacitance, then the read operation margin can be tested under severe conditions, but the testing accuracy is insufficient and cannot quantitatively measure the margin
Solution Approach 1:
The patent changes the parameter of the sense amplifier by adjusting its gain to create a controlled artificial margin. Instead of relying on physical cell variations, the invention uses gain adjustment as a controllable parameter to generate known margin conditions for quantitative testing. This allows precise control over the margin value being tested, enabling accurate measurement and comparison.
Solution Approach 2:
The patent creates a copy of the normal read operation by using a test mode that replicates the standard read sequence but with modified sense amplifier gain. This copied operation allows the margin to be tested under controlled conditions without affecting normal operation, and the results can be quantitatively compared against specifications.
2Reliability
If redundant memory cells are used for margin testing, then backup functionality is provided, but the load capacitance increases and access time slows down
Solution Approach 1:
The patent makes the sense amplifier universal by enabling it to perform both normal read operations and margin testing functions. The same sense amplifier circuit is used for both purposes, with the ability to switch between normal gain mode and reduced gain mode for testing. This eliminates the need for separate test circuits or redundant cells dedicated solely to testing, thereby avoiding the speed penalty of additional capacitive loads.
Solution Approach 2:
The normal memory cell structure and sense amplifier serve the dual purpose of data storage/reading and margin testing. The system uses itself for testing by internally generating test conditions through gain adjustment, rather than requiring external test equipment or additional dedicated test structures that would increase load capacitance.
3Measurement precision
If the sense amplifier gain is reduced to create artificial margin for testing, then quantitative margin testing becomes possible, but the normal read operation may be affected
Solution Approach 1:
The patent makes the sense amplifier gain dynamic rather than fixed. The gain can be adjusted based on the operating mode: normal gain for standard read operations and reduced gain for margin testing. This dynamic adjustment is controlled by mode selection signals that switch the sense amplifier between its normal function and test function, ensuring that each operation type uses the appropriate gain setting and neither interferes with the other.
Data Source
AI summary
A semiconductor memory device includes: a memory cell including a first cell that stores data, and a second cell that stores complementary data that is complementary to the data; a redundant memory cell including a third cell that stores margined complementary data in which a margin is added to the complementary data, and a fourth cell that stores margined data in which a margin is added to the data; and a controller that causes the data and the margined complementary data to be compared and a test of the first cell to be executed, and the complementary data and the margined data to be compared and a test of the second cell to be executed.