Memory Write Mask Alignment Using Matched Deserializers
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in maintaining high-speed operations while performing data masking operations, as timing alignment of mask patterns with data can be difficult to achieve, leading to reduced effective write cycles and overall operation speed.
Innovation Solution
The implementation of a semiconductor device with a first deserializer and a second deserializer, both configured to have matching timing characteristics, allows for time-aligned mask patterns and parallel data. This is achieved through a circuit structure that includes sampling, shift, and output stages, with clock signals generated based on a data strobe signal to control the loading time of data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data masking operation is performed in high speed memory device, then data writing capability is improved, but timing alignment between mask pattern and parallel data becomes difficult to achieve
Solution Approach 1:
The patent divides the data stream into multiple parallel data streams using a deserializer, and similarly divides the mask pattern into multiple parallel mask signals. This segmentation allows independent timing control of each data stream and mask signal, making it possible to achieve precise timing alignment between mask patterns and parallel data at different clock edges (e.g., rising edge and falling edge), thereby resolving the timing alignment difficulty while maintaining high-speed data writing capability
Solution Approach 2:
The patent employs dynamic clock signal generation where the clock signals used for mask pattern sampling are generated based on the data strobe signal with flexible phase relationships. The mask pattern sampling clock can be dynamically adjusted to align with either the rising edge or falling edge of the data clock, enabling adaptive timing alignment that maintains precision across varying operating conditions and speeds
2Productivity
If mask pattern is time-aligned with parallel data, then effective write cycle is enhanced, but device complexity increases
Solution Approach 1:
The patent designs the mask pattern sampling circuit to serve multiple functions: it can sample mask patterns at different clock edges (rising or falling), generate multiple mask signals simultaneously for different data streams, and adapt to different timing requirements. This multi-functionality allows a single circuit structure to achieve precise timing alignment and enhance effective write cycle without proportionally increasing device complexity
Solution Approach 2:
The patent uses replicated circuit structures where the same mask pattern sampling circuit is copied multiple times to handle different data streams in parallel. Each copy generates mask signals synchronized with its corresponding data stream, achieving timing alignment across all channels without requiring a single complex centralized control circuit, thus managing complexity through modular replication
Data Source
AI summary
Aspects of the disclosure provide a semiconductor device. For example, the semiconductor device can include a first deserializer, a second deserializer, and a write data converter coupled to the first deserializer and the second deserializer. The first deserializer can be configured to convert serial data to parallel data based on a set of write clock signals, thus the parallel data has a first timing alignment with regard to the set of write clock signals. The second deserializer can be configured to generate a mask pattern based on the set of write clock signals, thus the mask pattern has a second timing alignment with regard to the set of write clock signals. The write data converter can be configured to generate valid data based on the parallel data and the mask pattern.