3D-Stacked Memory Master Die Selection for Timing Margin Recovery
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Solution Overview
Problem
Conventional memory devices with three-dimensional stacks (3DS) of memory dies face challenges due to lack of control over process corners, leading to inadequate timing margins and unrecoverable failures when dies with opposite process characteristics are stacked, resulting in setup and hold data timing failures and increased fabrication costs.
Innovation Solution
Implementing post-packaging master die selection circuitry that enables any memory die with preferable design margins to serve as the master, allowing for dynamic selection and recovery by disabling faulty master dies, thereby reducing debug time and increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory dies with opposite process characteristics are stacked together in a 3DS, then manufacturing flexibility is improved, but timing margins become inadequate leading to setup and hold data timing failures
Solution Approach 1:
The patent implements dynamic master die selection capability that allows the system to adaptively choose which die serves as the master based on actual performance characteristics. The master selection circuitry can dynamically determine the optimal master die from multiple candidates in the stack, enabling the system to adjust to process variations and maintain adequate timing margins even when dies with opposite process characteristics are stacked together.
2Ease of manufacture
If conventional master die selection is used during packaging, then manufacturing process is simple, but unrecoverable failures occur when the selected master die is defective
Solution Approach 1:
The patent incorporates preliminary master die selection capability that evaluates multiple candidate dies before finalizing the master die selection. The master selection circuitry performs preliminary assessments of candidate dies' performance characteristics and readiness to serve as master, allowing the system to pre-identify and avoid defective master dies before they cause unrecoverable failures, while maintaining a relatively simple manufacturing process.
3Measurement precision
If debugging is performed on all possible fail modes, then comprehensive coverage is achieved, but debug time increases significantly
Solution Approach 1:
The patent extracts and isolates the master die selection function into dedicated master selection circuitry that can independently evaluate and select the optimal master die. This extraction allows debugging operations to focus specifically on the master selection logic and identified fail modes rather than examining all possible failure scenarios across the entire stack, thereby maintaining comprehensive debug coverage while significantly reducing debug time.
Data Source
AI summary
Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.