Memory Cell Mat Voltage Line Layout for Low-Resistance Power Supply
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Solution Overview
Problem
Forming connecting portions between via-conductors having a large diameter and lower wiring layers is difficult due to high line density, making it challenging to supply operating voltages to memory cell mats with low resistance.
Innovation Solution
Implementing a configuration where each memory cell mat is connected to a single via-conductor in a top wiring layer, with additional power supply lines in lower layers providing alternate pathways for array and ground potentials, ensuring stable supply without direct via-conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via-conductors having a large diameter are used to supply operating voltages with lower resistance, then electrical resistance is reduced, but the difficulty of forming connecting portions on lower wiring layers increases due to high line density
Solution Approach 1:
The patent transitions from a planar two-dimensional connection approach to a three-dimensional multi-layer approach. Instead of forming multiple large-diameter via-conductors on the same lower wiring layer, the invention uses a single large-diameter via-conductor connecting to multiple wiring layers above, creating vertical power supply paths that resolve the manufacturing difficulty while maintaining low resistance and high reliability.
2Reliability
If lines of upper layers with large line width are used to supply operating voltages, then electrical resistance is reduced, but the complexity of wiring layout increases due to high line density in lower layers
Solution Approach 1:
The patent utilizes the vertical dimension by extending power supply lines through multiple wiring layers (first, second, and third wiring layers) connected via via-conductors. This multi-layer vertical arrangement allows large line widths for low resistance without increasing planar layout complexity, as the power paths are distributed across different vertical levels rather than competing for horizontal space.
Solution Approach 2:
The power supply network is segmented into multiple independent wiring layers, each carrying specific power lines (first power supply lines, second power supply lines, third power supply lines). This segmentation allows each layer to be optimized independently, reducing overall wiring layout complexity while maintaining low resistance through adequate line widths in each segment.
Data Source
AI summary
Disclosed herein is an apparatus that includes: a memory cell array including a plurality of first memory cell mats arranged in a first direction; a first voltage line supplied with a first voltage, the first voltage line extending in the first direction and being connected to a plurality of first vias each arranged over a corresponding one of even numbered ones of the plurality of first memory cell mats; and a second voltage line supplied with a second voltage different from the first voltage, the second voltage line extending in the first direction and being connected to a plurality of second vias each arranged over a corresponding one of odd numbered ones of the plurality of first memory cell mats.