Memory-Matched LDPC Coding for Threshold-Specific Error Correction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current low-density parity-check (LDPC) coding schemes in data storage devices are not tailored to the specific memory error model, leading to inefficient error correction and increased memory overprovisioning due to a global error protection level that does not account for varying memory read thresholds.

Innovation Solution

The proposed solution involves using the memory error model during ECC construction and design, specifically applying a memory matching transform to convert data pages into transformed pages, where each read threshold introduces errors only in a subset of coded bits, allowing for parity bits to be determined and stored based on expected error rates, and using a memory matched LDPC encoder to encode these transformed pages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a global error protection level is used for LDPC coding, then error correction capability is maintained across all memory read thresholds, but memory overprovisioning increases and storage efficiency decreases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidmemory overprovisioning
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the error protection approach by creating separate LDPC coding schemes for different memory read thresholds. Each threshold has its own tailored error protection level, allowing optimization for specific error rates rather than using a single global protection level for all thresholds. This segmentation enables reduced overprovisioning while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by making error protection characteristics specific to each memory read threshold. Instead of uniform global protection, each threshold receives customized error protection tailored to its expected error rate, optimizing the balance between reliability and storage efficiency for different operational conditions.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If memory density is increased through process scaling and 3D stacking, then storage capacity is improved, but the media becomes noisier and error rates increase

Engineering Contradiction:
Improvememory capacityVSAvoiderror rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces dynamic adaptation by using memory error models that capture the actual error behavior of high-density media. The LDPC coding schemes are dynamically tailored to match the specific error characteristics of each memory read threshold, allowing the system to adapt to the increased noise in high-density media rather than using static global protection.

Inventive Principle:
Principle #15Dynamics

3Reliability

If ECC space is increased to improve error correction, then reliability is improved, but space available for user data decreases

Engineering Contradiction:
Improveerror correction capabilityVSAvoiduser data space
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent changes the parameters of the LDPC coding schemes to optimize the balance between ECC space and user data space. By tailoring coding parameters to each memory read threshold's error characteristics, the system achieves adequate error correction with minimized ECC overhead, maximizing space for user data.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11860733B2Memory matched low density parity check coding schemes
Publication Date: 2024.01.02 SANDISK TECHNOLOGIES LLC
  • US11860733B2 patent drawing
  • US11860733B2 patent drawing
  • US11860733B2 patent drawing

AI summary

Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.