Memory Array Matrix Fabric for Processor-Memory Wall
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Solution Overview
Problem
The existing processor-memory architectures face performance limitations due to the 'processor-memory wall,' where the physical interface between processors and memories acts as a bottleneck, limiting overall system performance despite advancements in processor and memory speeds.
Innovation Solution
The solution involves converting a memory array into a matrix fabric, allowing for matrix transformations and operations within the memory device. This is achieved by configuring an array of memory cells as a matrix multiplication unit (MMU) and using a memory sense component to read and write digital values based on matrix transformation opcodes and operands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional processor-memory architecture is used, then memory storage function is provided, but processor-memory interface acts as bottleneck limiting system performance
Solution Approach 1:
The patent merges processing functionality into the memory device by converting the memory array into a matrix fabric that can perform matrix transformations. This combines storage and computation functions, eliminating the need for complex processor-memory interfaces and overcoming the bottleneck limitation.
Solution Approach 2:
The memory device performs computational operations autonomously by configuring its own cells as a matrix multiplication unit. The memory array serves itself by executing matrix transformations without requiring external processor intervention, thereby improving system performance without increasing interface complexity.
2Productivity
If matrix operations are performed using iterative methods, then processing is completed, but processing time increases
Solution Approach 1:
The patent replaces iterative mechanical processing with parallel analog computation. The matrix fabric performs multiple matrix element computations simultaneously through parallel access to memory cells, substituting sequential iterative operations with concurrent analog calculations to reduce processing time.
Solution Approach 2:
The patent transitions from one-dimensional iterative processing to two-dimensional parallel computation by organizing memory cells into a matrix fabric structure. This dimensional reorganization enables simultaneous computation of multiple matrix elements, significantly reducing processing time while maintaining operational completeness.
Data Source
AI summary
Methods and apparatus for performing matrix transforms within a memory fabric. Various embodiments of the present disclosure are directed to converting a memory array into a matrix fabric for matrix transformations and performing matrix operations therein. Exemplary embodiments described herein perform matrix transformations within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). In one exemplary embodiment, the matrix fabric uses a “crossbar” construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage. The resulting signals can be converted from analog voltages to digital values by an MMU to yield a vector-matrix product. In some cases, the MMU may additionally perform various other logical operations within the digital domain.