Memory Matrix With Vertical Transistors
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Solution Overview
Problem
Existing memory matrices aim to minimize the average area per bit, but there is a desire to further reduce this ratio while maintaining efficient data storage and access.
Innovation Solution
The proposed electronic circuit design incorporates vertical transistors with two resistive memory elements per access transistor, sharing a single control electrode, and utilizes distinct voltages on second row conductors to minimize power consumption and area requirements, allowing for independent information storage with minimal area penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical transistors are used with two resistive memory elements per access transistor, then the average area per bit is reduced, but the device complexity increases
Solution Approach 1:
Two resistive memory elements are combined under a single access transistor, sharing the same control electrode. This merging approach allows both memory elements to be accessed through one transistor, reducing the overall area per bit while the shared control mechanism manages the increased device complexity
Solution Approach 2:
The access transistor serves multiple functions by controlling access to two different resistive memory elements. This multi-functionality is achieved through selective voltage application to different row conductors, allowing one transistor to efficiently manage multiple storage elements without proportionally increasing control circuit complexity
2Use of energy by moving object
If distinct voltages are applied to second row conductors during access, then power consumption is reduced, but the control circuit complexity increases
Solution Approach 1:
Different voltage levels are applied to different second row conductors based on their specific function during access operations. Selected row conductors receive one voltage level while unselected rows receive different voltage levels, creating localized voltage conditions that minimize parasitic currents and reduce overall power consumption
Solution Approach 2:
The control circuit implements periodic voltage switching to row conductors during access operations. By applying distinct voltages in a controlled sequence - first to selected rows, then to unselected rows - the system minimizes simultaneous current paths and reduces power consumption while managing control complexity through time-multiplexed voltage application
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the average area per bit while maintaining efficient data storage and access, achieving power savings through optimized voltage application and resistive memory element usage.
Implementation Method 1
A phase change material is provided on top of the body. The resistance of the material phase change material depends on the waveform applied during a last write action.
Implementation Method 2
The cell is read by measuring the resistance between the column conductors when the row conductor of a selected row is driven so that the access transistors in a selected row become conductive.
Data Source
Figure 1~2
Figure 3a~3b
Figure 4~5
AI summary
An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.