Memory Built-In Self-Test Status Using a Select DMI Bit

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Solution Overview

Problem

Existing memory devices face challenges in efficiently performing memory built-in self-tests (MBIST) after integration into memory systems, particularly when time constraints are critical, and using multiple data mask inversion (DMI) pins leads to increased signaling complexity and potential errors.

Innovation Solution

The solution involves using a single select DMI bit to indicate the status of MBIST, allowing the host device to monitor a single bit for MBIST performance, reducing the need for additional pins and signaling complexity while maintaining reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple DMI pins are used to indicate MBIST status, then the indication capability is improved, but the signaling complexity and potential errors increase

Engineering Contradiction:
ImproveMBIST status indication reliabilityVSAvoidsignaling complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the MBIST status indication function with the existing DMI pin functionality. Instead of adding separate pins for MBIST status indication, the invention reuses the DMI pin to carry both data mask inversion control and MBIST status information, thereby reducing signaling complexity while maintaining reliability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The DMI pin is designed to serve multiple functions: it acts as both the data mask inversion control signal and the MBIST status indication signal. This multi-functionality eliminates the need for additional dedicated pins for MBIST status, reducing overall device complexity while preserving the reliability of status indication.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple DMI pins are used to indicate MBIST status, then the indication capability is improved, but the potential for errors increases

Engineering Contradiction:
ImproveMBIST status indication reliabilityVSAvoidsignaling errors
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

By combining MBIST status indication with the existing DMI pin control signal, the invention reduces the number of signal lines that could potentially cause errors. Fewer pins mean fewer potential failure points in the signaling path, thereby reducing the likelihood of signaling errors while maintaining reliable status indication.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If a single DMI bit is used to indicate MBIST status, then the pin requirements are reduced, but the indication capability must be maintained

Engineering Contradiction:
Improvepin requirementsVSAvoidMBIST status indication reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The invention makes the DMI pin universal by enabling it to perform both its original data mask inversion function and the additional MBIST status indication function. This multi-functionality allows a single pin to provide comprehensive control and status information without requiring additional pins, thereby reducing device complexity while maintaining indication reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250299763A1Indicating a status of a memory built-in self-test using a data mask inversion bit
Publication Date: 2025.09.25 MICRON TECHNOLOGY INC
  • US20250299763A1 patent drawing
  • US20250299763A1 patent drawing
  • US20250299763A1 patent drawing

AI summary

Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test using a data mask inversion (DMI) bit. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first DMI bit of the memory device that is associated with indicating a status of the memory built-in self-test and a second DMI bit of the memory device that is not associated with indicating the status of the memory built-in self-test. The memory device may set the first DMI bit to a first value based on the one or more bits indicating that the memory built-in self-test is enabled. The memory device may perform the memory built-in self-test based on setting the first DMI bit to the first value.