Multi-Tier Memory Media Access for In-Memory Compute Management
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Solution Overview
Problem
Memory controllers are unable to effectively manage memory media when unaware of memory access operations, leading to potential interruptions of ongoing operations and inefficient wear leveling.
Innovation Solution
The implementation of media access circuitry that performs compute operations locally within the memory media, allowing for independent management of memory access operations, wear leveling, and reference voltage adjustments, thereby offloading tasks from the memory controller and enabling in-memory computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory controller manages all memory access operations centrally, then it can track memory accesses for wear leveling and reference voltage adjustment, but it cannot perform compute operations locally without interrupting ongoing memory operations
Solution Approach 1:
The patent divides memory management into two independent segments: the memory controller handles traditional memory management tasks (wear leveling, reference voltage adjustment), while the media access circuitry handles compute operations and local memory access. This segmentation allows both components to function independently without interfering with each other's operations.
Solution Approach 2:
The media access circuitry acts as an intermediary between the processor and memory media, performing compute operations locally and managing its own memory access operations. This intermediary role eliminates the need for the memory controller to be involved in compute operations, reducing its complexity while maintaining full memory management capability.
2Use of energy by moving object
If compute operations are performed in the memory media, then power usage and bus usage are reduced, but the memory controller becomes unaware of ongoing operations and cannot effectively manage the memory media
Solution Approach 1:
The media access circuitry is designed to be self-sufficient, independently tracking its own memory access operations, performing wear leveling, and adjusting reference voltages for the memory media it manages. This self-service capability ensures reliable memory management even when the memory controller is unaware of ongoing compute operations.
Solution Approach 2:
The patent creates independent management domains where the media access circuitry manages compute-related memory operations and the memory controller manages traditional memory operations. Each segment maintains full awareness and control of its designated functions, ensuring reliability without requiring centralized knowledge of all operations.
3Reliability
If the memory controller tracks all memory accesses for wear leveling, then wear distribution is optimized, but the controller cannot independently manage compute operations without interrupting memory operations
Solution Approach 1:
The patent separates wear leveling functionality into two independent components: the memory controller performs wear leveling for traditional memory operations, while the media access circuitry performs wear leveling for compute operations. This segmentation allows both to optimize wear distribution for their respective operation types without interfering with each other's productivity.
Solution Approach 2:
The media access circuitry serves as an intermediary that independently manages wear leveling for compute operations, eliminating the need for the memory controller to track and manage compute-related memory accesses. This intermediary approach maintains wear leveling effectiveness while enabling efficient compute operations without interruptions.
Data Source
AI summary
Technologies for providing multiple tier memory media management include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory compute operation. Additionally, the media access circuitry is to read, in response to the request, data from a memory media region of the memory media, write the read data into a compute media region of the memory, perform, on the data in the compute media region, the in-memory compute operation, write, to the memory media region, resultant data indicative of a result of performance of the in-memory compute operation.