Memory Metadata Address Mapping for Faster Column-Plane Access

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Solution Overview

Problem

The storage and retrieval of metadata in semiconductor memory devices is time-consuming due to the need for multiple steps to locate its storage location, which is inefficient in terms of hardware complexity and time consumption.

Innovation Solution

Implementing an internal metadata address generator to map metadata addresses using a subset of column addresses, allowing metadata to be stored and retrieved in parallel with data across multiple column planes, thereby reducing the need for full column address usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metadata is stored in the memory array with data, then metadata can be stored and retrieved, but multiple steps are required to locate the metadata storage location which increases time consumption and hardware complexity

Engineering Contradiction:
Improvemetadata storage capabilityVSAvoidmetadata retrieval time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the memory array into distinct data regions and metadata regions, allowing independent addressing. Metadata is stored in separate locations that can be directly accessed without searching through data regions, thereby reducing retrieval time while maintaining reliable storage capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an address generation mechanism that acts as an intermediary to directly compute metadata addresses from data addresses. This intermediary system eliminates the need for sequential searching or multiple access steps, reducing time consumption while ensuring accurate metadata retrieval.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple steps are used to locate metadata storage location, then metadata can be found, but hardware complexity increases

Engineering Contradiction:
Improvemetadata location accuracyVSAvoidaddressing mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements preliminary address calculation where metadata addresses are computed in advance and stored in association with data addresses. This preliminary action eliminates the need for complex runtime searching mechanisms, reducing hardware complexity while maintaining accurate metadata location capability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables the addressing system to self-generate metadata addresses from data addresses using deterministic algorithms. This self-service mechanism eliminates the need for external control logic or complex addressing hardware, reducing device complexity while ensuring reliable metadata location.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If full column address is used for metadata addressing, then accurate metadata location is achieved, but hardware complexity and time consumption increase

Engineering Contradiction:
Improvemetadata address precisionVSAvoidaddressing mechanism complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts only the necessary portion of the column address (e.g., lower-order bits) for metadata addressing, rather than using the full column address. This extraction approach maintains sufficient address precision for metadata location while significantly reducing the complexity of the addressing mechanism and associated hardware.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12488815B2Apparatuses, systems, and methods for managing metadata storage at a memory
Publication Date: 2025.12.02 MICRON TECHNOLOGY INC
  • US12488815B2 patent drawing
  • US12488815B2 patent drawing
  • US12488815B2 patent drawing

AI summary

Apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. A metadata column address generator, during a metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. A column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address.