Memory Metal Scheme for Control Line Resistance Reduction
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Solution Overview
Problem
As semiconductor memory devices shrink in size and increase in density, the resistance of signal paths increases, leading to a speed bottleneck due to narrow control signal lines, particularly in advanced technology nodes where word line resistance is 2.5 times higher than in previous nodes, necessitating the use of word line repeaters that increase layout area and power consumption.
Innovation Solution
Implementing multiple metal layers for control lines in the same direction to reduce resistance without increasing layout area, by strategically using metal layers M2, M3, and M4, and employing vias to connect these lines, thereby improving memory operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If signal path size is reduced to increase memory density, then memory density is improved, but signal path resistance increases causing speed bottleneck
Solution Approach 1:
The patent transitions from planar (2D) signal routing to three-dimensional (3D) signal routing by utilizing multiple metal layers stacked vertically. Control lines are distributed across different metal layers (M2, M3, M4) and connected through vias, creating a spatially distributed network that reduces the effective path length and resistance while maintaining high memory density.
2Productivity
If control signal line width is reduced to increase functional density, then functional density is improved, but resistance increases leading to speed bottleneck
Solution Approach 1:
The patent employs multiple metal layers (M2, M3, M4) stacked in the vertical dimension to route control signals. By distributing control lines across multiple layers and connecting them via vias, the effective cross-sectional area for signal transmission increases, thereby reducing resistance without reducing functional density.
3Speed
If word line resistance is reduced by using wider lines, then speed is improved, but layout area increases
Solution Approach 1:
The patent utilizes the vertical dimension by implementing control lines across multiple metal layers (M2, M3, M4) stacked above each other. This 3D routing approach effectively increases the conductive cross-section and reduces resistance without expanding the planar layout area, as the additional conductive paths are arranged vertically rather than horizontally.
4Speed
If word line repeaters are added to reduce resistance, then speed is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent replaces the need for word line repeaters by implementing a multi-layer metal routing scheme. By distributing control lines across multiple metal layers and using vias to connect them, the design achieves low resistance signal paths through spatial distribution rather than through active repeater circuits, thereby reducing device complexity and power consumption.
Data Source
AI summary
A method of fabricating a memory array includes designing first layout sections in a row direction, each first layout section including first and second control lines in a first metal layer, and an upper conductive line in a third metal layer. A lower conductive line in a second metal layer is coupled to the first control line and the first control line is isolated from the second control line. A second layout section is inserted at every N-th first layout section, N being a positive integer equal to or greater than 2. The second layout section includes the first control line, the second control line and a lower conductive line in the second metal layer coupled to the second control line and to an upper conductive line in the third metal layer. The lower conductive lines in the first and second layout sections are isolated from each other.