Semiconductor Memory Apparatus Mirror Mode Control
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Solution Overview
Problem
Current semiconductor memory systems require additional channels or interfaces for mirror mode operations, increasing costs and limiting the simultaneous performance of other RAS features, such as availability and serviceability.
Innovation Solution
A semiconductor memory apparatus with multiple memory apparatuses that can independently operate in different modes, including a normal mode, mirror mode, and spare mode, using command and chip select signals to manage data input/output operations across multiple ranks or channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If mirror mode is performed using additional channel or interface chip, then reliability is improved, but system cost increases
Solution Approach 1:
The patent merges the mirror mode functionality into the existing memory apparatus without requiring additional interface chips or channels. The first and second memory apparatuses share common control logic and data buses, allowing redundancy to be achieved through software/firmware coordination rather than hardware duplication. This integration eliminates the need for separate mirror mode interface circuits while maintaining reliability benefits.
Solution Approach 2:
The memory apparatus is designed with universal control circuits that can handle multiple operation modes (normal mode, mirror mode, spare mode) using the same hardware infrastructure. The control logic can dynamically switch between different modes of operation without requiring mode-specific hardware components, thereby reducing system cost while maintaining reliability through configurable redundancy operations.
2Reliability
If mirror mode is performed, then reliability is improved, but other RAS features cannot be simultaneously performed
Solution Approach 1:
The patent implements dynamic mode switching capability where the memory system can transition between normal mode, mirror mode, and spare mode based on operational requirements. The control logic dynamically allocates resources and configures data paths in real-time, allowing the system to adapt between different RAS features without hardware conflicts. This dynamic reconfiguration enables flexible deployment of reliability and availability features as needed.
Solution Approach 2:
The memory apparatus is segmented into functionally independent first and second memory apparatuses that can operate in different modes simultaneously or be coordinated through control logic. This segmentation allows the system to partition operations such that one memory apparatus handles primary operations while the other provides redundancy or supports different RAS features, enabling simultaneous performance of multiple RAS capabilities through coordinated operation of separate memory units.
3Reliability
If additional channel or interface chip is used for mirror mode, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges mirror mode functionality into the existing memory apparatus without requiring additional interface chips or channels. The first and second memory apparatuses share common control logic and data buses, allowing redundancy to be achieved through software/firmware coordination rather than hardware duplication. This integration eliminates the need for separate mirror mode interface circuits while maintaining reliability benefits.
Data Source
AI summary
A semiconductor memory apparatus may include a first memory apparatus and a second memory apparatus, and may perform various operation modes. The first and second memory apparatuses may independently perform a write operation and a read operation in a first operation mode. The first memory apparatus may perform a write operation and a read operation and the second memory apparatus may perform a write operation in a second operation mode. The second memory apparatus may perform a write operation and a read operation in a third operation mode.