Memory Mirroring via Single Write Operation

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Solution Overview

Problem

Conventional memory mirroring techniques in server systems require additional channel bandwidth and power, and result in inefficient memory utilization due to the need for separate write operations and unused memory slots, leading to suboptimal performance and capacity utilization.

Innovation Solution

The implementation of a memory system that allows duplicate copies of a data element to be stored in different memory locations using a single write operation, with signal latency adjustments enabling concurrent writing across multiple modules within a channel, thereby eliminating the need for additional bandwidth and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional memory mirroring techniques are used with separate write operations, then memory reliability is improved through backup storage, but channel bandwidth consumption increases and memory utilization becomes inefficient

Engineering Contradiction:
Improvememory reliabilityVSAvoidmemory utilization efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines multiple separate write operations into a single concurrent write operation that simultaneously stores data in both primary and backup memory locations. This merging approach maintains memory reliability through backup storage while eliminating the need for additional channel bandwidth and improving memory utilization efficiency by avoiding wasted memory slots.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If separate write operations are used for primary and backup memory, then data redundancy is ensured, but power consumption increases

Engineering Contradiction:
Improvedata redundancyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent merges separate write operations for primary and backup memory into a single concurrent write operation. This approach ensures data redundancy is maintained while significantly reducing power consumption by eliminating the need for multiple separate write cycles and their associated power requirements.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If additional channel bandwidth is allocated for memory mirroring, then backup memory access is enabled, but overall system performance deteriorates

Engineering Contradiction:
Improvebackup memory accessVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent combines backup memory access with primary memory access into a single concurrent write operation using the same channel bandwidth. This eliminates the need for additional channel bandwidth allocation while maintaining backup memory access capability, thereby preserving overall system performance.

Inventive Principle:
Principle #5Merging (Combining)

4Reliability

If memory slots are reserved for backup memory, then memory reliability is improved, but available memory capacity decreases

Engineering Contradiction:
Improvememory reliabilityVSAvoidavailable memory capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines primary and backup memory operations into a single concurrent write that utilizes existing memory slots efficiently. This approach maintains memory reliability through backup storage while maximizing available memory capacity by avoiding wasted slots that would result from reserved dedicated backup memory regions.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11106542B2Memory mirroring
Publication Date: 2021.08.31 RAMBUS INC
  • US11106542B2 patent drawing
  • US11106542B2 patent drawing
  • US11106542B2 patent drawing

AI summary

Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.