Memory Mode Register Command Disabling Mechanism
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
During command training for DRAM devices, misinterpretation of commands as vendor-specific or PPR commands can lead to unnecessary remapping of memory rows, consuming valuable spare resources and putting the memory device in an undefined state that may not recover from a reset.
Innovation Solution
Implementing a mechanism to disable specific commands, such as the PPR command, by using a sticky bit in the mode register that remains set until a reset or power-cycle event occurs, preventing unintended execution of these commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If command training is performed by testing the command bus using functional write/read traffic, then the command bus can be trained and timing/voltage can be margined, but a bad command may be accidentally received as a PPR command causing fuse burning and device failure
Solution Approach 1:
The mode register is configured to disable the PPR command before command training begins. This preliminary disabling prevents any accidental PPR command execution during the training process, eliminating the risk of fuse burning while allowing comprehensive command bus testing to proceed
Solution Approach 2:
The mode register acts as an intermediary control mechanism that filters and controls command execution. By setting specific bits in the mode register, the system mediates between the command bus input and the PPR command execution, allowing only intentionally enabled PPR commands to be executed while blocking accidental ones during training
2Ease of repair
If a complete reset is performed when a failure is detected during training, then the memory device can be recovered, but the device may be put in an undefined state that reset does not recover
Solution Approach 1:
The PPR command is disabled in advance before any failure can occur during training. This preliminary protective action prevents the device from entering the harmful undefined state that would otherwise require reset recovery, ensuring the device remains in a stable, known good state throughout training
3Adaptability or versatility
If PPR resources are used for real repairs, then memory rows can be remapped to spare rows, but precious PPR resources may be accidentally consumed leading to no resources left for real repairs
Solution Approach 1:
The mode register is configured to disable the PPR command before training begins, preventing accidental consumption of PPR resources. This ensures that all PPR resources remain available for their intended purpose of repairing actual manufacturing defects, while still allowing comprehensive command bus training to be performed
Data Source
Figure 1
Figure 2
Figure 3
AI summary
In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.