Memory Mode Registers with Preloaded Parameter Codes for Fast Switching
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Solution Overview
Problem
Changing memory operating conditions to accommodate different clock frequencies requires multiple mode register write operations, which can delay memory operation and complicate control, especially when multiple parameters need to be changed simultaneously.
Innovation Solution
The implementation of mode registers that store multiple parameter codes for operating and control parameters, along with control parameters to select and switch between these codes quickly, allowing simultaneous switching of memory conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple mode register write operations are performed to change memory operating parameters, then the memory can operate at different clock frequencies, but the operation is delayed and control is complicated
Solution Approach 1:
The patent segments the parameter codes for different operating parameters into separate storage locations within the mode register, allowing individual parameters to be accessed and changed independently. This segmentation enables selective updating of only the necessary parameters rather than requiring multiple sequential write operations for all parameters, thereby reducing operation delay while maintaining the ability to adapt to different clock frequencies
Solution Approach 2:
The patent implements preliminary action by pre-configuring the mode register with default parameter codes for different operating conditions. When a clock frequency change is required, the system can quickly switch between pre-stored parameter sets rather than performing multiple write operations in real-time. This preliminary preparation eliminates operation delays and simplifies control by allowing instant switching between predefined operating states
2Adaptability or versatility
If multiple parameter codes are written sequentially to mode registers, then memory operating parameters can be changed, but the control process becomes complicated
Solution Approach 1:
The patent merges multiple parameter codes into a single mode register structure, where different parameter codes for various operating parameters (such as burst length, latency, termination settings) are stored in different fields or locations within the same register. This consolidation allows all necessary parameter changes to be performed through a single write operation rather than multiple sequential operations, significantly simplifying the control process while maintaining full adaptability for configuring memory operating parameters
Solution Approach 2:
The mode register is designed with multi-functionality to handle various operating parameters through a unified interface. The register can store and switch between different parameter codes for burst length, preamble/postamble length, read/write latencies, on-die termination settings, and reference voltage settings all through the same register write operation. This universal approach simplifies control by providing a single point of access for configuring multiple operating parameters simultaneously
Data Source
AI summary
Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.


