Memory Programming Mode Transitions for Constant Host Data Transfers
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Solution Overview
Problem
Traditional caching-based architectures in memory sub-systems lead to throttling and command collisions due to limited cache buffer memory and increased power-fail hold-up requirements, resulting in higher system costs and data blocking issues.
Innovation Solution
Implementing a queuing mechanism and timed data transfer system to manage transitions among atomic programming modes, allowing commands to be accepted without immediate data recording, and scheduling data transfers based on media unit availability to reduce cache buffer memory and power-fail hold-up requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache buffer memory size is increased to handle write workloads exceeding media bandwidth, then data transfer capability is improved, but system cost and power-fail hold-up requirements increase
Solution Approach 1:
The patent implements dynamic programming mode transitions (SLC/MLC/TLC/QLC) that allow the memory system to adaptively adjust data transfer capabilities based on workload conditions. The controller dynamically switches between different programming modes with varying bandwidth characteristics, eliminating the need for permanently oversized buffer memory while maintaining the ability to handle peak write workloads.
Solution Approach 2:
The system changes operational parameters by transitioning between different atomic programming modes (SLC, MLC, TLC, QLC) with different data transfer characteristics. This allows the memory sub-system to accommodate variable data transfer sizes without requiring fixed large buffer memory, thereby reducing system cost and power-fail hold-up requirements while maintaining productivity.
2Speed
If traditional caching architecture is used to isolate host system from memory sub-system, then data access speed is improved, but buffer memory consumption and command collisions increase
Solution Approach 1:
The patent implements preliminary scheduling of data transfers between host system and memory sub-system. The data transfer manager pre-schedules transfers based on media unit availability, allowing non-blocking and out-of-order command processing. This eliminates command collisions while maintaining high data access speed without requiring large buffer memory.
Solution Approach 2:
The patent introduces a data transfer manager as an intermediary that schedules and coordinates data transfers between the host system and memory sub-system. This mediator manages programming mode transitions and accommodates constant data transfer sizes, eliminating the need for traditional large cache buffer memory while maintaining fast data access through efficient scheduling.
3Ease of operation
If write commands are processed in-order through traditional cache, then command processing simplicity is maintained, but command collisions and data storage time in buffer increase
Solution Approach 1:
The data transfer manager performs preliminary scheduling of write commands based on media unit availability before actual data transfer. This advance planning enables out-of-order processing that eliminates command collisions and reduces data storage time in buffer, while maintaining operational simplicity through centralized schedule management.
Solution Approach 2:
The system implements dynamic command processing that transitions between in-order and out-of-order execution based on scheduling conditions. The data transfer manager adaptively manages programming mode transitions and data transfer timing, allowing the system to maintain ease of operation while eliminating the time losses associated with command collisions and prolonged buffer storage.
Data Source
AI summary
A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.