Hardware Memory Model Full Erase Verification
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Solution Overview
Problem
Current design verification processes for circuit designs with memory devices are bottlenecked by the slow cycle-by-cycle erasing method, particularly evident in large complex designs like System-on-Chip, where erasing a 2-GB memory instance can take over 30 minutes, hindering productivity.
Innovation Solution
A reconfigurable hardware modeling device is programmed to implement a hardware model of a circuit design with a memory system that allows for a full-memory erase operation by changing a global memory status value, enabling a single sub-operation to erase all memory sectors, rather than the conventional sector-by-sector approach, thereby speeding up the erase process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional cycle-by-cycle erasing method is used, then each memory sector is erased individually ensuring complete erasure, but the run time for erasing a whole memory card becomes extremely long (over 30 minutes for 2-GB memory)
Solution Approach 1:
The patent segments the memory erasure process into two distinct levels: a global memory status value that applies to the entire memory card, and individual sector status values for each sector. This segmentation allows the system to perform a single global erase operation that logically erases all sectors simultaneously, while still maintaining the ability to track and manage individual sector states if needed. The global memory status value changes upon a full-memory erase operation, providing a efficient way to erase entire memory cards without iterating through each sector individually.
Solution Approach 2:
The patent implements a logical erasure mechanism where changing the global memory status value to indicate erasure is sufficient for verification purposes, even if individual sector data remains physically present. This partial action approach is sufficient for design verification where the goal is to confirm erasure functionality rather than actually clearing all physical data. The system performs more than enough erasure action (changing global status) to satisfy verification requirements without the excessive time cost of complete physical erasure of every sector.
2Measurement precision
If a conventional cycle-by-cycle erasing method is used, then accurate memory state tracking is maintained, but verification productivity is significantly reduced due to the bottleneck in erase operations
Solution Approach 1:
The patent segments the memory erasure process into two distinct levels: a global memory status value that applies to the entire memory card, and individual sector status values for each sector. This segmentation allows the system to perform a single global erase operation that logically erases all sectors simultaneously, while still maintaining the ability to track and manage individual sector states if needed. The global memory status value changes upon a full-memory erase operation, providing a efficient way to erase entire memory cards without iterating through each sector individually.
Solution Approach 2:
The patent introduces an intermediary mechanism - the global memory status value - that mediates between the erase operation and the individual sectors. Instead of directly interacting with each sector during erasure, the system uses this global status value as an intermediary to represent the erasure state of the entire memory card. This intermediary approach maintains accurate state tracking while dramatically improving productivity by avoiding the need to process each sector individually.
3Reliability
If a full-memory erase operation is performed using traditional methods, then all memory sectors are erased, but the process requires extensive sector-by-sector operations that slow down verification
Solution Approach 1:
The patent segments the memory erasure process into two distinct levels: a global memory status value that applies to the entire memory card, and individual sector status values for each sector. This segmentation allows the system to perform a single global erase operation that logically erases all sectors simultaneously, while still maintaining the ability to track and manage individual sector states if needed. The global memory status value changes upon a full-memory erase operation, providing a efficient way to erase entire memory cards without iterating through each sector individually.
Solution Approach 2:
The patent merges the erasure operation into a single global action that affects the entire memory card at once, rather than requiring separate operations for each sector. By combining all sector erasure operations into one unified global memory erase command, the system achieves full-memory erasure with minimal complexity. The hardware model updates the global memory status value to reflect the erasured state, providing a simple yet reliable mechanism that avoids the complexity of managing individual sector erasure operations.
Data Source
AI summary
A hardware model of a memory comprises: first circuitry configured to supply a memory status value for the memory which is changed upon a full-memory erase operation; second circuitry configured to supply a sector status value for each memory sector of the memory which is changed to a value equal to the memory status value when a write operation is performed on the each memory sector of the memory; and third circuitry configured to supply, when a read operation is performed on a memory sector of the memory, a value stored in the memory sector as output of the read operation if the sector status value for the memory sector is equal to the memory status value or a predefined value as the output of the read operation in other situations.