Memory Module Alert Signal Termination for SODIMM Integrity

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Solution Overview

Problem

In memory modules, long signal lines for alert signals lead to signal reflections, causing distortions in the waveform of alert signals, which complicates the system structure and affects signal integrity, especially in SODIMMs with various configurations like 1 DPC and 2DPC.

Innovation Solution

A semiconductor device with a memory module that includes a plurality of memory chips with alert terminals, a first transmission line connected to each memory chip, an alert signal output terminal connected to one end of the line, and a termination resistor connected to the other end, reducing signal reflections and distortions by effectively terminating the signal line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a long signal line is used to connect alert terminals of multiple memory chips, then the memory module can support more memory chips and complex system structures, but signal reflections occur causing waveform distortions

Engineering Contradiction:
Improvesupport for more memory chipsVSAvoidsignal integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies parameter changes by introducing termination resistors with specific resistance values (e.g., 50 ohms, 100 ohms) at strategic positions along the signal line. These resistance parameters are carefully selected to match the characteristic impedance of the transmission line, thereby eliminating signal reflections and maintaining waveform integrity while supporting long signal lines with multiple memory chips.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The termination resistor acts as an intermediary element between the signal source and the load. It mediates the signal transmission by absorbing excess energy and preventing reflections, thus enabling long signal lines to operate reliably without compromising signal quality or causing waveform distortions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a termination resistor is added to reduce signal reflections, then signal integrity is improved, but device complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoidnumber of components
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by placing termination resistors at specific locations along the signal line rather than uniformly throughout. The resistors are positioned at critical points where reflections are most likely to occur, such as near the load or at intermediate points, thereby achieving effective signal termination with minimal additional components and reduced overall complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution significantly reduces waveform distortions of alert signals, maintaining signal integrity and ensuring proper alert signal transmission to the memory controller, even in complex system structures like SODIMMs, by optimizing the termination resistance and line configurations.

Implementation Method 1

a problem in which alert signals reflect on the signal line will occur

Methodology Applied
Scientific EffectSignal reflection: Reflection

Implementation Method 2

a first termination resistor connected to another end of the first transmission line

Methodology Applied
Scientific EffectImpedance matching: Electrical Impedance Tomography

Data Source

PatentUS9524756B2Apparatuses and methods for coupling semiconductor devices of a memory module in a memory system
Publication Date: 2016.12.20 MICRON TECHNOLOGY INC
  • US9524756B2 patent drawing
  • US9524756B2 patent drawing
  • US9524756B2 patent drawing

AI summary

A system includes memory chips mounted on a memory module each having an alert terminal that notifies that the memory chip has detected a predetermined error. The memory module has a first transmission line connected to alert terminals of memory chips, output terminal being connected to one end of the first transmission line, and a first termination resistor having an end connected to another end of the first transmission line. The system further includes a second transmission line having an end connected to the alert terminal and another end connected to a controller and a third transmission line having an end connected to a first input terminal on the memory module and a second end line and a second end having a voltage different from a voltage of another end of the first termination resistor.